VME interface
We don’t have enough pins for a full VME interface in the AFPGA, therefore the SVEC7 will use a low pin count inter-FPGA link to tunnel the VME traffic through the SFPGA. The pins are described in the table below:
All pins use the SSTL15 I/O standard, reusing the power supply/Vref of the DDR3 memory.
-
Please use the supplied XDC file for the pin assignment in the AFPGA. -
On the SFPGA side, power an entire bank from 1.5V and supply the 0.75V Vref. -
All signals must be terminated on the far side (check Xilinx UG471). -
The RSVD lines between the AFPGA and SFPGA can be dropped.
The 1.5V SFPGA bank can be also used for DIP switches (SWITCH0..1, NOGA0..5) and debug LEDs.