Skip to content

Documentation-related issues

Common thread for all coding style and documentation-related issues:

Reported by Maciek Lipinski:

  • Some text is upside down, correct
  • Update description (right bottom corner) on pages 17-21
  • FMC slot 1, green letters indicating connectors are incorrect for "I" and "J", should be "J" and "K" instead, the same problem with connector names J2I and J2J, should be J2J and J2K (pdf page 5, sheet 10)
  • FMC slot 2, ideally, the naming of connectors would be consistent, i.e. replace "J3D", "J3C", "J3B", and "J3A" with "J3H", "J3G", "J3B" and "J3A". (pdf page 5, sheet 10)

Reported by Dimitris Lampridis:

General:

  • On all pages, fix template info at bottom right. Project name, page description, EDA number, people, dates, etc.

  • The following pages use a different (and empty) template as well:

    • DDR3 SODIMM
    • AFPGA_FMC1_FMC2
    • Slow_IO_Mux
    • AFPGA_MISC
    • AFPGA_1V0

  • Fix the warnings reported by Altium after compilation (very few, nice!). If any is acceptable, use a targeted no-ERC directive.

  • Is there any particular reason why some nets have labels and others don't?

Top-level schematic:

  • For the serial interface between the FPGAs, put a red "title" in the SFPGA block and change the "user switches" red title in the AFPGA block to something meaningful. I also guess that the rogue "user switches" red title at 4700,3700mil is from the SFPGA block.

  • In the serial interface between FPGAs the _I and _O suffixes (and the whole RX/TX) on the net labels are confusing. I would go for something explicit like bridge_s2a_dat, bridge_a2s_dat and bridge_a2s_clk or something similar. I would use the same scheme in the HDL of both FPGAs as well (with _i and _o in those).

  • some diff signals have the differential directive on the top-level, others don't (they have it inside some sheet of course). I'd prefer to stick with one approach, either all on the top level, or all at the source (or all at the destination).

  • I would use more harnesses, especially for things like the two identical sets of FMC signals between AFPGA <-> FMC slots <-> GTP.

  • I would rearrange the sheets and connections so that the Front Panel and FMC slots are the last blocks on the right side of the page, with ports only on the left side of these sheet symbols. It makes sense (to me at least): from VME on the left, through VME buffers, FPGAs, to the front panel and FMC slots on the right.

  • I would "hide" the FPGA power sheets under their respective FPGA top-level sheets. After all, they are pins/sub-parts of the FPGA.

  • Is there any particular reason why some nets have labels and others don't?

AFPGA:

  • It would be nice to mention the FPGA banks used in each sheet symbol here, as well as the VCCIO of each bank.

DDR3 SODIMM:

  • Several DDR signals are active-low but their net labels lack the _N suffix.

  • It is not immediately clear if SK1A is the top or bottom row of the DIMM socket.

  • Also it is weird that a) we have two symbols, IC24 and SK1, with IC24 exactly on top of SK1 and b) IC24 has no pins but all the signal names, while SK1 is the opposite.

  • Missing differential directives on diff pairs

  • Rename sheet to show that the bridge signals are also here.

  • Missing no ERC on SODIMM CK1 pins.

AFPGA FMC1 FMC2:

  • Any particular reason that the FMC pin order and slots are mixed? Does it help with layout?

Slow I/O Mux;

  • This IMHO should be hierarchically "under" the AFPGA Misc sheet, not on the same level as the other AFPGA sheets, because it does not contain any FPGA bank on itself and its ports would be better grouped together with those of the AFPGA Misc sheet (e.g. the "FMC1 & FMC2" ports could join the "FMC1" and "FMC2" port groups in the AFPGA Misc sheet symbol).

AFPGA Misc:

  • Use capital letters for all ports

FPGA GTP:

  • I would put the Kintex7 banks 115 and 116 hierarchicaly under the AFPGA sheet.

JTAG & SFPGA Flash:

  • Rename sheet to remove the "SFPGA" from it, this now also has the AFPGA config.

  • I would put the Kintex7 bank 0 hierarchicaly under the AFPGA sheet.

Reported by Christos Gentsos:

General:

  • Page info has been left outdated, in some pages it's unpopulated

DDR3_SODIMM:

  • The net DDR3_RESET should be renamed to DDR3_RESET_N, it's active low. Also assuming that it's tied low to keep the RAM asleep until the FPGA is up and running?
  • RAS/CAS/CS/WE signals are always low so there's no confusion but maybe their nets should get the _N, too, for consistency

Slow_IO_MUX:

  • The IOEXP_CLK_INH and IOEXP_SH/LD ports could be moved to the component above to slightly improve readability

AFPGA_Misc:

  • There are many nets that are labeled while only connected to hierarchical ports; the labels could be removed for less clutter

JTAG chain + SFPGA flash

  • It might be a good idea to move AFPGA above SFPGA, since it comes first in the JTAG chain.

VME_connectors

  • Plenty of active-low signals are missing the _N but I don't know this isn't common notation in this specific case, just noting

Reported by Tom:

  • SFP port (113) names don't match with the FPGA GTX transceiver quad (115)
  • Be consistent with IC names (ICxx or Uxx, we prefer ICxx).
  • BOOT_CW port/BOOT_SW signal - keep the naming consistent.
Edited by Tomasz Wlostowski