FPGA Bank Assignment
![image](data:image/gif;base64,R0lGODlhAQABAAAAACH5BAEKAAEALAAAAAABAAEAAAICTAEAOw==)
Notes:
- Swapping within banks (14, 16) and (12, 13, 15) is allowed, except for the clock lines or signals connected to
global/regional clock input.
- Swapping in the DDR3 bank is allowed within byte groups (i.e. within DQ[0..7], DQ[8..15] etc)