V3 - Replace DDR3 memory by DDR3 SO-DIMM module
- With the new 1/2GSPS 8-bit ADC mezzanines, the memory bandwidth of the two 16-bit DDR chips used currently on the SVEC carrier  is insufficient.
- Xilinx's DDR3 controller performance is quite low compared to alternatives.
- DDR3 chips are getting difficult to obtain.
- Remove the two DDR3 chips from the SVEC.
- Connect a DDR3 SO-DIMM module socket instead with 64-bit data path width (some pin swapping/reassignment might be needed).
- Evaluate the performance of the LiteDRAM controller with AXI4-full host interface, port it to SVEC AFPGA and validate with the SO-DIMM module .
- Provide proof-of-concept VHDL/Verilog code.