... | ... | @@ -26,7 +26,7 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
|
|
- No dedicated clock signals from Carrier to FMC (as only
|
|
|
available on HPC pins and use LPC)
|
|
|
- FMC connectivity: all 34 differential pairs connected, 1 GTP
|
|
|
transceiver with clock, 2 clock pairs, JTAG
|
|
|
transceiver with clock, 2 clock pairs, JTAG, I2C
|
|
|
- Xilinx FPGAs
|
|
|
- Application FPGA: Spartan-6 XC6SLX150T-3FGG900C
|
|
|
- Direct connection to all resources such as VME64x, memories
|
... | ... | @@ -230,5 +230,5 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
|
|
|
|
|
-----
|
|
|
|
|
|
Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 26 November 2014
|
|
|
Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 29 September 2015
|
|
|
|