hdl/top/sfpga_bootloader: pulse PLL_CE pin on startup to avoid potential CDCM61004 PLL locking issues

top: updated ISE projects to use latest versions of submodules (general-cores & vme64x-core). Added synthesis descriptor in the golden bitstream.

- update on the Golden Core registers (memory map + block diagram)
- info for Windows user on preparing flash images
- added git version to the title page

hdl/top/sfpga_bootloader: added power-on reset circuit (fixes rare issues with invoking the bootloader for the 1st time)

top/golden: fixed I2C bus ordering bug, replaced OpenCores's I2C master with the Golden bistream core

The column signals where not properly driven, preventing to light the led independantly.

An address counter is automatically incremented on data r/w.

Add ddr test testbench to repo.