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@@ -23,34 +23,42 @@ Latin.
 ## Main Features
 
   - 4-lane PCIe (Gennum GN4124)
+  - 1x Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C) 
   - FMC slot with low pin count (LPC) connector
       - Vadj fixed to 2.5V
-      - No dedicated clock signals from Carrier to FMC (only available
-        on HPC pins)
-      - LPC cheaper than HPC and also easier to mount
       - FMC connectivity: all 34 differential pairs connected, 1 GTP
         transceiver with clock, 2 clock pairs, JTAG
-  - 1 Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C) 
+      - No dedicated clock signals from Carrier to FMC (only available
+        on HPC pins)
   - Simple clocking resources
-      - 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
-      - 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
-      - 1 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)
-      - 1 low-jitter frequency synthesizer (TI CDCM61004, fixed
-        configuration, Fout=125MHz)
+      - 1x 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs
+        Si570)
+      - 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
+        used by [White Rabbit PTP
+        core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
+      - 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
+        used by [White Rabbit PTP
+        core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
+      - 1x low-jitter frequency synthesizer (TI CDCM61004, fixed
+        configuration, Fout=125MHz, used by [White Rabbit PTP
+        core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
   - On board memory
-      - A 2Gbit DDR3
-      - 1 SPI 32Mbit flash PROM for multiboot FPGA powerup
+      - 1x 2Gbit (256 MByte) DDR3 (MT41J128M16JT-125)
+      - 1x SPI 32Mbit flash PROM for multiboot FPGA powerup
         configuration, storage of the FPGA firmware or of critical data 
+  - Miscellaneous
+      - on-board thermometer IC (DS18B20U+)
+      - unique 64-bit identifier (DS18B20U+)
   - Front panel containing
-      - 1 Small Formfactor Pluggable (SFP) cage for fibre-optic
-        transceiver
-        ([WhiteRabbit](https://www.ohwr.org/project/white-rabbit)
-        support) 
-      - Programmable LED
+      - 1x Small Formfactor Pluggable (SFP) cage for fibre-optic
+        transceiver ([WhiteRabbit
+        support](https://www.ohwr.org/project/white-rabbit)). 1.25 and
+        2.5 Gbps.
+      - Programmable Red and Green LEDs
       - FMC front panel
   - Internal connectors
-      - 1 JTAG header for Xilinx programming during debugging
-      - 1 mini USB AB (USB-UART bridge)
+      - 1x JTAG header for Xilinx programming during debugging
+      - 1x mini USB AB (USB-UART bridge)
   - FPGA configuration. The FPGA can optionally be programmed from:
       - GN4124 SPRIO interface (loaded by software driver at startup)
       - JTAG header
@@ -107,13 +115,15 @@ Latin.
   - [Design Information](DesignInfo)
   - [Software](Software)
   - [Users](Users)
-  - [Frequently Asked
-    Questions](FAQ)
+  - [Frequently Asked Questions](FAQ)
 
 -----
 
 ## Releases
 
+  - Hardware: [SPEXI
+    V1](https://www.ohwr.org/project/spexi/wikis/documents)
+
 -----
 
 ## Contacts