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![](/uploads/e62f4d86e09945dd15a6390b1c8c4dde/spexi_v1_small.jpg)
*SPEXI v1**
**SPEXI v1**
## Main Features
- 4-lane PCIe (Gennum GN4124) *obsolete component, not available
- 4-lane PCIe (Gennum GN4124) *obsolete component, not available
anymore*
- 1x Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C)
- FMC slot with low pin count (LPC) connector
- Vadj fixed to 2.5V
- FMC connectivity: all 34 differential pairs connected, 1 GTP
transceiver with clock, 2 clock pairs, JTAG
- No dedicated clock signals from Carrier to FMC (only available
- 1x Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C)
- FMC slot with low pin count (LPC) connector
- Vadj fixed to 2.5V
- FMC connectivity: all 34 differential pairs connected, 1 GTP
transceiver with clock, 2 clock pairs, JTAG
- No dedicated clock signals from Carrier to FMC (only available
on HPC pins)
- Simple clocking resources
- 1x 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs
- Simple clocking resources
- 1x 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs
Si570)
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
used by [White Rabbit PTP
core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
used by [White Rabbit PTP
core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed
core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\))
- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed
configuration, Fout=125MHz, used by [White Rabbit PTP
core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core\)))
- On board memory
- 1x 2Gbit (256 MByte) DDR3 (MT41J128M16JT-125)
- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup
configuration, storage of the FPGA firmware or of critical data
(M25P128-VMF6G)
- Miscellaneous
- on-board thermometer IC (DS18B20U+)
- unique 64-bit identifier (DS18B20U+)
- Front panel containing
- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic
- On board memory
- 1x 2Gbit (256 MByte) DDR3 (MT41J128M16JT-125)
- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup
configuration, storage of the FPGA firmware or of critical data (M25P128-VMF6G)
- Miscellaneous
- on-board thermometer IC (DS18B20U+)
- unique 64-bit identifier (DS18B20U+)
- Front panel containing
- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic
transceiver ([WhiteRabbit
support](https://www.ohwr.org/project/white-rabbit)). 1.25 and
2.5 Gbps. Note: WR is *not* supported by the LabVIEW drivers.
- Programmable Red and Green LEDs
- FMC front panel
- Internal connectors
- 1x JTAG header for Xilinx programming during debugging
- 1x mini USB AB (USB-UART bridge)
- FPGA configuration. The FPGA can optionally be programmed from:
- GN4124 SPRIO interface (loaded by software driver at startup)
- JTAG header
- SPI 32Mbit flash PROM
- selectable by GN4124 GPIO. Default option would be loading via
- Programmable Red and Green LEDs
- FMC front panel
- Internal connectors
- 1x JTAG header for Xilinx programming during debugging
- 1x mini USB AB (USB-UART bridge)
- FPGA configuration. The FPGA can optionally be programmed from:
- GN4124 SPRIO interface (loaded by software driver at startup)
- JTAG header
- SPI 32Mbit flash PROM
- selectable by GN4124 GPIO. Default option would be loading via
the SPI flash PROM (stand-alone applications).
- Debugging features
- mini USB connector
- 4 LEDs
- 2 buttons
- Optimised for cost
- 8-layer PCB
- Debugging features
- mini USB connector
- 4 LEDs
- 2 buttons
- Optimised for cost
- 8-layer PCB
## PXIe specific features
\* PXI express form factor, 3U high, single slot
\* Clock and synchronisation back plane signals
* PXI express form factor, 3U high, single slot
* Clock and synchronisation back plane signals
|**PXI clock and synchronisation signals**|**PXI express clock and synchronisation signals**|
|----|----|
......@@ -94,23 +93,19 @@ Latin.
## Project information
- Official production documentation: [EDMS
EDA-02839](http://edms.cern.ch/nav/EDA-02839/)
- [CERN specific information](CERN)
- [Design Information](DesignInfo)
- [Software](Software)
- [Users](Users)
- [Frequently Asked Questions](FAQ)
- Official production documentation: [EDMS EDA-02839(http://edms.cern.ch/nav/EDA-02839/)
- [CERN specific information](CERN)
- [Design Information](DesignInfo)
- [Software](Software)
- [Users](Users)
- [Frequently Asked Questions](FAQ)
Since the SPEXI is a board which is based on the design of the
[SPEC](https://www.ohwr.org/project/spec/wiki), some of the
documentation of the SPEC can also be used:
- [Getting Started with the
SPEC](https://www.ohwr.org/project/spec-getting-started/wiki)
(project)
- [SPEC Frequently Asked
Questions](https://www.ohwr.org/project/spec/wikis/FAQ)
- [Getting Started with the SPEC](https://www.ohwr.org/project/spec-getting-started/wiki) (project)
- [SPEC Frequently Asked Questions](https://www.ohwr.org/project/spec/wikis/FAQ)
-----
......@@ -118,14 +113,12 @@ documentation of the SPEC can also be used:
### Hardware
- Official production documentation: [EDMS
EDA-02839](http://edms.cern.ch/nav/EDA-02839/)
- Pre-release design documentation:
[SPEXI-V1.0.zip](https://www.ohwr.org/project/spexi/uploads/dd19b51611639085e51bd8c332f305e4/SPEXI-V1-0.zip)
- Official production documentation: [EDMS EDA-02839](http://edms.cern.ch/nav/EDA-02839/)
- Pre-release design documentation: [SPEXI-V1.0.zip](https://www.ohwr.org/project/spexi/uploads/dd19b51611639085e51bd8c332f305e4/SPEXI-V1-0.zip)
### FPGA examples (including the .ucf-file)
- [spexi\_simpledemo.zip](https://www.ohwr.org/project/spexi/uploads/aae580fa08bec2ca351fbf70d323f802/spexi_simpledemo.zip)
- [spexi\_simpledemo.zip](https://www.ohwr.org/project/spexi/uploads/aae580fa08bec2ca351fbf70d323f802/spexi_simpledemo.zip)
The file **spexi\_simpledemo.zip** contains a demo design and all
the files including the .bit and .msc files which can be used to
download this design to the SPEXI using Xilinx iMPACT and the
......@@ -139,9 +132,7 @@ documentation of the SPEC can also be used:
the Spartan-6
150T.
<!-- end list -->
- [spexi\_golden.zip](https://www.ohwr.org/project/spexi/uploads/49147527317a03356b8fc9e0a1b9db55/spexi_golden.zip)
- [spexi\_golden.zip](https://www.ohwr.org/project/spexi/uploads/49147527317a03356b8fc9e0a1b9db55/spexi_golden.zip)
The file **spexi\_golden.zip** contains the same design as
**spexi\_simpledemo.zip** but does not contain the GPIO register for
the LEDs and buttons. This design is used to be able to get the
......@@ -149,9 +140,7 @@ documentation of the SPEC can also be used:
which other FMC specific FPGA design could be loaded
safely.
<!-- end list -->
- [spexi\_pts.zip](https://www.ohwr.org/project/spexi/uploads/748fbd2f4a56afbba23ddd48e6c7ed39/spexi_pts.zip)
- [spexi\_pts.zip](https://www.ohwr.org/project/spexi/uploads/748fbd2f4a56afbba23ddd48e6c7ed39/spexi_pts.zip)
The file **spexi\_pts.zip** contains the complete set of VHDL/FPGA
designs and corresponding phyton files for the [Production Test
Suite](https://www.ohwr.org/project/pts). This PTS is used to test
......@@ -165,14 +154,13 @@ documentation of the SPEC can also be used:
### Commercial producers
- [SPEXI](http://www.incaacomputers.com/products/spexi/) [INCAA
Computers](http://incaacomputers.nl), Netherlands.
- [SPEXI](http://www.incaacomputers.com/products/spexi/) [INCAA Computers](http://incaacomputers.nl), Netherlands.
### General question about project
- [Adriaan Rijllart](mailto:Adriaan.Rijllart@cern.ch) - CERN - project
- [Adriaan Rijllart](mailto:Adriaan.Rijllart@cern.ch) - CERN - project
initiator
- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
-----
......@@ -216,6 +204,4 @@ documentation of the SPEC can also be used:
-----
Erik van der Bij, Adriaan Rijllart - 8 September 2017
Erik van der Bij, Adriaan Rijllart - 8 September 2017
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