Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
S
SPEC7
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
4
Issues
4
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
SPEC7
Issues
Open
4
Closed
28
All
32
New issue
Recent searches
Press Enter or click to search
{{hint}}
{{tag}}
{{name}}
@{{username}}
No Assignee
{{name}}
@{{username}}
No Milestone
Upcoming
Started
{{title}}
No Label
{{title}}
{{name}}
Yes
No
Created date
Priority
Created date
Last updated
Milestone
Due date
Popularity
Label priority
SPEC7 SN05 FLASH programming
#32
· opened
Jul 27, 2022
by
Peter Jansweijer
CLOSED
1
updated
Nov 04, 2022
Intel discontinuation of DC/DC convertors
#31
· opened
Sep 29, 2021
by
Peter Jansweijer
0
updated
Sep 29, 2021
PCB stackup GND2 => 2V5
#30
· opened
Sep 29, 2021
by
Peter Jansweijer
0
updated
Sep 29, 2021
D72 and D74 (near PLL LTC6950) not visible under custom heatsink.
#29
· opened
Aug 19, 2021
by
Peter Jansweijer
0
updated
Aug 19, 2021
USB type A obsolete ( TE 1932638)
#28
· opened
May 03, 2021
by
Guido Visser
CLOSED
1
updated
May 24, 2021
Add 5A "Ideal Diode" in 12V FMC power line
#27
· opened
Jan 28, 2021
by
Peter Jansweijer
CLOSED
1
updated
Jan 29, 2021
Vivado Critial Warnings
#26
· opened
Jan 27, 2021
by
Peter Jansweijer
CLOSED
0
updated
Jan 27, 2021
Specify connector gold for BullsEye J4
#25
· opened
Jan 20, 2021
by
Peter Jansweijer
CLOSED
1
updated
Mar 25, 2021
ESD protection chip IP3319CX6 is a nightmare when replacing is needed.
#24
· opened
Dec 08, 2020
by
Peter Jansweijer
CLOSED
1
updated
Feb 23, 2021
JTAG issue Pin 1
#23
· opened
Oct 22, 2020
by
Guido Visser
CLOSED
1
updated
Feb 23, 2021
SPEC7 v2 QPLL / CPLL use
#22
· opened
Oct 12, 2020
by
Peter Jansweijer
CLOSED
2
updated
Dec 14, 2020
Schematic,direction of arrows at sfp+ Wrong
#21
· opened
Oct 05, 2020
by
Guido Visser
CLOSED
1
updated
Dec 04, 2020
PUDC_B is floating. not allowed.
#20
· opened
May 29, 2020
by
Guido Visser
CLOSED
0
updated
Dec 04, 2020
Route BE_REFCLK_P/N input back to outout on the bullseye
#19
· opened
May 27, 2020
by
Guido Visser
CLOSED
1
updated
Mar 19, 2021
Soft start 3V3_FMC
#18
· opened
May 17, 2020
by
Peter Jansweijer
CLOSED
0
updated
Dec 04, 2020
LTC6950 dissipation
#17
· opened
May 17, 2020
by
Peter Jansweijer
2
updated
Jan 20, 2021
ESD protection CP2105 (U54, dual UART)
#16
· opened
May 17, 2020
by
Peter Jansweijer
CLOSED
5
updated
Feb 17, 2021
"Soft" reset to FPGA
#15
· opened
Mar 19, 2020
by
Peter Jansweijer
CLOSED
1
updated
Dec 08, 2020
BullsEye SPARE_P/N outputs always disabled
#14
· opened
Feb 25, 2020
by
Peter Jansweijer
CLOSED
0
updated
Dec 03, 2020
PPS_OUT wrongly reclocked when BE_REFCLK is used as 125 MHz refclk (using HPSEC)
#13
· opened
Feb 24, 2020
by
Peter Jansweijer
CLOSED
2
updated
Dec 04, 2020
Prev
1
2
Next
