specgather.md

@@ -8,7 +8,23 @@ specification of the SPEC7.
 ### FMC HPC or LPC
 
   - use case for HPC?
+      - HPC would be interesting for some applications like high-speed
+        ADCs where you need to go massively parallel to avoid too high
+        bandwidth requirements on the data lines.
   - Makes that large FPGA should be used
+  - HPC: need new tests tools for production test
+
+Price idea:
+
+  - LPC ($12.68/connector), n layers, Kintex 70T FPGA
+  - HPC ($20.40/connector), n+2 layers, Kintex 325T FPGA -\> 325T? 160T
+    not large enough?
+
+<!-- end list -->
+
+  - use case for LPC
+      - Existing FMC mezzanines: DIO, ADC100M, TDC, Fine Delay,
+        masterFIP
 
 ### FMC connector
 
@@ -27,7 +43,8 @@ specification of the SPEC7.
   - Kintex 7
       - FBG676 package allows 70T, 160T, 325T and 410T sizes on the same
         footprint. 
-          - Default 160T. 
+          - Default 160T: XC7K160T-2FBG676C ([on
+            ECIAauthorized](https://www.eciaauthorized.com/en/search/XC7K160T-2FBG676C))
           - 8 GTX Transceivers max (4 used for PCIe, 2 for SFP, 2 left
             for FMC).
           - Check if a 70T in FBG484 package can be used on footprint of
@@ -66,10 +83,13 @@ specification of the SPEC7.
 
   - SO-DIMM socket for RAM
   - Or directly assembled RAM IC?
+  - Use case: data memory for storing data coming from ADC card (e.g.
+    [fmc-adc-100m14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki)
 
 ### FLASH storage
 
   - MicroSD slot?
+  - eMMC ?
 
 ### USB
 
@@ -78,12 +98,36 @@ specification of the SPEC7.
     should rename the card to SPUEC or SUPEC (U for USB). Perhaps this
     is a crazy idea, but it is nice to think that users can plug'n'play
     the SPUEC/SUPEC on their laptop :) (FV)*
+  - The current mini-USB can serve two UARTs if we use a [CP2105 - Dual
+    UART
+    bridge](https://www.silabs.com/documents/public/data-sheets/CP2105.pdf).
+    Quite handy if you have a WRPC gui and other logic in your FPGA. 
+      - Need two mini-USB connectors then, isn't it?
 
 ### PCB
 
   - 10 layer PCB so that layout can be optimised for low-jitter
     oscillator
 
+### Other remarks from NIKHEF
+
+Some extra's that were on our list:
+
+1.  We need high performance timing-IO signals (including absolute
+    calibration signals) on (accessible) connectors. The current DIO is
+    really bad for timing. We (Guido) should look into this. A possible
+    candidate is a Samtec Bulls-Eye which is just a land pattern on your
+    PCB. But we should study this since a Bulls-Eye is the perfect phase
+    plane reference but the phase plane will not be very accessible from
+    the outside world (i.e. on the PCI bracket). 
+2.  Timing signals should be re-clocked with high speed FFs outside the
+    FPGA. I remember that this was an issue that you CERN guys also
+    proposed earlier.
+3.  We need to think of some digital interface (including connectors) to
+    close an external PLL loop using an external high performance
+    oscillator. Ideas are still vague at this moment but the interface
+    as such should already be on the list.
+
 -----
 
 ## Accepted
@@ -95,6 +139,7 @@ specification of the SPEC7.
         panel-mounted).
       - Planned to be used on SPEC for daisy-chaining triggers between
         SPECs with FMC-ADCs with modified gateware.
+      - May be used as well for digital interface for external PLL loop
 
 -----