specgather.md

@@ -10,8 +10,8 @@ SPEC7.
 
 #### NIKHEF/JRP, CERN: as high-precision PCIe and stand-alone White Rabbit design
 
-\* Aim: White Rabbit node with target frequency instability of 1e-13
-over 100 sec.
+\* Aim: new PCIe FMC carrier that is optimised as White Rabbit node with
+a target frequency instability of 1e-13 over 100 sec.
 
 \* Users will be first: research institutes and metrology institutes
 with the aim to disseminate UTC from metrology partners to European
@@ -32,12 +32,16 @@ timing performance.
 \* Priority
 
 1.  optimise for performance
+      - Try out ideas of presentation [*High quality standard standard
+        frequency
+        transfer*](https://www.ohwr.org/project/white-rabbit/uploads/7163913a8935a3ef6cf912e22b90a3da/6_hp-mr.pdf),
+        2016, NIKHEF & CERN
 2.  (cost)
 
 #### CERN: as SPEC replacement
 
-\* Aim: smooth replacement of existing SPEC that is a cheap FMC carrier
-with WR support.
+\* Aim: smooth replacement of existing SPEC that is a cheap *Simple FMC
+carrier with WR support*.
 
 * The existing SPEC with WRS are the two flagship OH projects and the
 SPEC7 therefore may not fail as project.
@@ -95,8 +99,8 @@ alternative.
           - cf.
             [XC6SLX45T-3FGG484C](https://www.eciaauthorized.com/en/search/XC6SLX45T-3FGG484C)
             on SPEC: (~84 Euro without STEP pricing)
-          - 8 GTX Transceivers max (4 used for PCIe, 2 for SFP, *only 2
-            left for FMC*).
+          - 8 GTX Transceivers max (4 used for PCIe, 1 for SFP, *only 3
+            left for FMC and SATA*).
               - A 70T in FBG484 package cannot be used as has only 4 GTX
                 Transceivers (No need to check if can be used on
                 footprint of FBG676)
@@ -116,6 +120,7 @@ alternative.
             Euro)
           - [XC7A100T-2FGG676C](https://www.eciaauthorized.com/en/search/XC7A100T-2FGG676C)
             (~180 Euro)
+      - FBG484 package allows only 4 GTX transceivers (x1 PCIe?).
 
 <!-- end list -->
 
@@ -200,6 +205,12 @@ alternative.
     bridge](https://www.silabs.com/documents/public/data-sheets/CP2105.pdf).
     Quite handy if you have a WRPC gui and other logic in your FPGA. 
 
+### SATA
+
+  - Proposed Xilinx has only 8 GTX Transceivers max (4 used for PCIe, 1
+    for SFP, *only 3 left for FMC and SATA*), so should not have SATA
+    anymore?
+
 ### PCB
 
   - 10 layer PCB so that layout can be optimised for low-jitter
@@ -251,5 +262,5 @@ Some extra's that were on our list:
 
 -----
 
-24 January 2018
+25 January 2018