... | @@ -35,8 +35,7 @@ |
... | @@ -35,8 +35,7 @@ |
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configuration, Fout=125 MHz, used by [White Rabbit PTP
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configuration, Fout=125 MHz, used by [White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
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- On board memory
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- On board memory
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- 1x SO-DIMM socket standard mounted with **xx** Gbit (**xx**
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- 1x 8Gbit (1 GByte) DDR3 IC
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MByte) DDR3
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- MicroSD slot for flash memory
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- MicroSD slot for flash memory
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- 1x SPI **xx** Mbit flash PROM for multiboot FPGA powerup
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- 1x SPI **xx** Mbit flash PROM for multiboot FPGA powerup
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configuration, storage of the FPGA firmware or of critical data
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configuration, storage of the FPGA firmware or of critical data
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... | @@ -52,16 +51,15 @@ |
... | @@ -52,16 +51,15 @@ |
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- FMC front panel
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- FMC front panel
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- Internal connectors
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- Internal connectors
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- 1x JTAG header for Xilinx programming during debugging
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- 1x JTAG header for Xilinx programming during debugging
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- 2x SATA connector
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- 2x 14-pin header connector
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- Default connected to buffered LVDS general purpose I/O
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- Default connected to buffered LVDS general purpose I/O
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- With Z035 version may be connected to GTX (in which case no
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- With Z035 version may be connected to GTX (in which case no
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additional 2 GTX on FMC connector)
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additional 2 GTX on FMC connector)
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- 1x mini USB AB (USB-UART bridge)
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- 1x mini USB AB (USB-UART bridge)
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- Footprint for High-speed connector for PPS in/out, 10MHz in,
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- Samtec Bulls-Eye connector (just a land pattern for [22 signals
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tx-abscal, rx-abscal, refclock. 6 signals to be transferred in a
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on the PCB](https://www.samtec.com/products/bara)).
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differential way Samtec Bulls-Eye connector (just a land pattern
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- For PPS in/out, 10MHz in, tx-abscal, rx-abscal, refclock. 6
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for [22 signals on the
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signals to be transferred in a differential way
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PCB](https://www.samtec.com/products/bara)).
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- FPGA configuration. The FPGA can optionally be programmed from:
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- FPGA configuration. The FPGA can optionally be programmed from:
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- JTAG header
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- JTAG header
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- SPI 32Mbit flash PROM
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- SPI 32Mbit flash PROM
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... | @@ -86,7 +84,6 @@ |
... | @@ -86,7 +84,6 @@ |
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including possibility of two or four extra GTX lines with Z035
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including possibility of two or four extra GTX lines with Z035
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upgrade)
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upgrade)
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- Possibility of double PCIe bandwidth (2 GByte/s with Z035 upgrade)
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- Possibility of double PCIe bandwidth (2 GByte/s with Z035 upgrade)
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- DDR3 on SO-DIMM socket (reduces obsolescence, allows larger memory)
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- MicroSD slot for flash memory
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- MicroSD slot for flash memory
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- SFP+ at maximum 10 Gbps, instead of SFP at max 2.5 Gbps
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- SFP+ at maximum 10 Gbps, instead of SFP at max 2.5 Gbps
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- Improved oscillators for lower jitter White Rabbit
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- Improved oscillators for lower jitter White Rabbit
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... | @@ -95,10 +92,10 @@ |
... | @@ -95,10 +92,10 @@ |
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## Lost functionality
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## Lost functionality
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- SATA connectors are not connected to GTX lines on default Z030
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- SATA connectors replaced by 14-pin headers. LVDS, GPIO connected,
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Xilinx but to buffered LVDS.
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not to GTX anymore
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- With Z035 SATA possibility to order connection to GTX (default
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- PCB board size likely will be larger (not compatible to existing
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buffered LVDS).
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boxes?)
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-----
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-----
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... | @@ -123,8 +120,10 @@ Alternative Xilinx Zynq series with ARM processor integrated: |
... | @@ -123,8 +120,10 @@ Alternative Xilinx Zynq series with ARM processor integrated: |
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(Xilinx list prices compared for additional cost)
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(Xilinx list prices compared for additional cost)
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Total: *with all options, 115 Euro extra cost (Xilinx, HPC), total cost
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Total: *with all options, 115 Euro extra cost (Xilinx, HPC,
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price 295 Euro.* (cf. 180 SPEC without PCB and front-panel)
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oscillators), total cost price 325 Euro.* (cf. 180 SPEC). Prices without
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PCB and front-panel.
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PCB will also be more expensive (likely larger, more layers)
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-----
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-----
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... | | ... | |