Home.md

@@ -2,10 +2,14 @@
 
 ## Project description
 
-The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an
-SFP connector. This board is optimised for cost and is usable with most
+*The FMC PCIe Carrier called SPEC7 is an FMC carrier that can hold one
+FMC card and an SFP connector.**  
+This board is optimised for low jitter and cost and is usable with most
 of the FMC cards designed within the OHR project (e.g. ADC cards, Fine
 Delay).  
+The design is done in a collaboration between
+[NIKHEF](https://www.nikhef.nl/en/) (NL) and CERN as both need a card
+with a similar functionality.
 
 The SPEC7 is the follow-up of the
 [SPEC](https://www.ohwr.org/project/spec/wiki) of which the design
@@ -18,33 +22,134 @@ Express bus ([SPEXI - Simple PXI express FMC Carrier Board
 Other FMC projects and the FMC standard are described in [FMC
 Projects](https://www.ohwr.org/project/fmc-projects).
 
-## Main Features - *Under discussion*
+-----
 
-  - [Specification gathering discussion](specgather) - a list of wish
-    items ...
-  - [Feature Alternatives](FeatureAlternatives) - boiling down to a few
-    alternatives ...
-  - [Design specification](DesignSpecification) - to a precise
-    specification that allows the design to start
+## Main Features
+
+  - 2-lane PCIe Gen2
+      - Same 1 GByte/s total speed as 4-lane PCIe Gen1 on SPEC. Bridge
+        integrated in FPGA
+  - Xilinx Zynq FPGA with ARM processor
+        integrated
+      - [XC7Z030-1FBG676C](https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf)
+        (-1= slowest, commercial temp range, fast enough for most
+        applications) 
+          - 4 GTX receivers (2 used for PCIe, 1 for SFP, 1 for FMC -
+            same as on SPEC) 
+      - Possibility to mount Z035: XC7Z035-1FBG676C or XC7Z045-1FBG676C
+          - 8 GTX receivers (2 used for PCIe, 1 for SFP, 5 for FMC)
+  - FMC slot with high pin count (HPC) connector
+      - Vadj programmable at 1.8V and 2.5V
+          - 2.5V can only be used with a LPC FMC mezzanine: only the LPC
+            pins (LA bank) are 2.5V tolerant.
+      - Fully populated LA bank
+          - All 34 differential pairs connected, 1 GTP transceiver with
+            clock, 2 clock pairs, JTAG, I2C (as on SPEC)
+      - Limited, partial connectivity of HPC part, 1.8V tolerant only
+          - **xx** signals on HA bank
+          - HA bank only 1.8V tolerant (Vadj set to 1.8V)
+          - only when Xilinx Z035 or Z040 is mounted, the DP1\_M2C/C2M
+            and DP2\_M2C/2CM are connected to two GTX transceivers 
+  - Clocking resources
+      - 1x Fixed frequency oscillator for Application processor unit
+        (APU) (frequency?)
+      - 1x 10-280 MHz VCXO controlled by I2C and a DAC with SPI
+        interface. Starts up at 100 MHz (Silicon Labs Si571, freely
+        usable)
+      - 1x 125 MHz TCXO controlled by a DAC with SPI interface (used by
+        [White Rabbit PTP
+        core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
+        (Crystek CVPD-922 model)
+      - 1x 124.992 MHz VCXO controlled by a DAC with SPI interface (used
+        by [White Rabbit PTP
+        core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
+        (Crystek CVPD-922 model)
+  - On board memory
+      - 1x 8 Gbit (1 GByte) DDR3 IC connected to the Memory Interface
+        (main use for the APU)
+          - a 4 GByte SO-DIMM module cannot be used: has 64-bit
+            interface, while the FGPA can only handle 32-bits and1 GByte
+            max)
+      - 1x 8 Gbit (1 GByte) DDR3 IC connected to the programmable logic
+          - for bandwidth reasons
+      - 1x SPI **xx** Mbit flash PROM for multiboot FPGA powerup
+        configuration, storage of the FPGA firmware
+      - 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing
+        serial number, calibration parameters and other critical data
+        such as the MAC address of the card
+      - 64 MB static memory (needed for booting?) 
+      - MicroSD slot for flash memory for storing programs 
+  - Miscellaneous
+      - Thermometer and semi-unique ID provided by the FPGA)
+  - Front panel containing
+      - 1x Small Formfactor Pluggable+ (SFP+) cage for fibre-optic
+        transceiver
+        ([WhiteRabbit](https://www.ohwr.org/project/white-rabbit)
+        support). 1.25, and 2.5 Gbps
+      - Programmable Red and Green LEDs
+      - FMC front panel
+  - Internal connectors
+      - 1x JTAG header for Xilinx programming during debugging
+      - 1x USB-C connector
+          - Can serve two UARTs over the same single mini-USB connector
+            with CP2105 - Dual UART bridge IC
+              - One to UART interface of the ARM, one to user logic
+                (e.g., PTP core)
+      - 1x USB-C connector connected to USB port of the ARM
+      - Samtec Bulls-Eye connector ([22 signals on the
+        PCB](https://www.samtec.com/products/bara), 6 cm2 land pattern,
+        user mountable connector)
+          - For PPS in/out, 10MHz in, tx-abscal, refclock. 5 signals to
+            be transferred in a differential way
+          - ESD protection on all signals
+      - Ethernet RJ45 connector + magnetics and PHY (interface to ARM
+        GigE)
+  - 1x connector for optional cooling fan
+  - FPGA configuration. The FPGA can optionally be programmed from:
+      - JTAG header
+      - SPI **xx** Mbit FLASH PROM
+      - User FPGA logic: via PCIe or ARM (i.e. using [Internal
+        Configuration Access Port:
+        ICAPE2](https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf))
+  - Stand-alone features
+      - External 12V power supply connector
+      - USB-C connector
+      - Ethernet
+      - 4x LEDs
+      - 2x buttons
+          - 1 connected to reset controller
+          - 1 general purpose
+  - Power consumption: 5-12 Watt, depending on application
+  - Optimised for cost
+      - 8-layer PCB 
+  - Optional cooling fan for the mezzanine
 
 -----
 
 ## Project information
 
   - Official production documentation
+  - Design Specification
+      - [Specification gathering discussion](specgather) - a list of
+        wish items ...
+      - [Feature Alternatives](FeatureAlternatives) - ... boiling down
+        to a few alternatives ...
+      - [Design specification](DesignSpecification) - ... to a precise
+        specification that allows the design to start. A cleaned-up
+        version can be found on this very page at [Main
+        Features](/wiki#main-features). 
   - [Users](Users)
   - [Frequently Asked Questions](FAQ)
 
 -----
 
-## Releases
-
------
-
 ## Contacts
 
 ### Commercial producers
 
+  - Once designed and debugged, the board will be commercially
+    available.
+
 ### General questions about project
 
   - [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
@@ -83,10 +188,15 @@ Projects](https://www.ohwr.org/project/fmc-projects).
 <td>18-05-2018</td>
 <td><a href="FeatureAlternatives">Feature Alternatives</a> clarified at 2-day visit from NIKHEF and Tsinghua University at CERN to result in the [Design specification](DesignSpecification).</td>
 </tr>
+<tr class="even">
+<td>28-05-2018</td>
+<td><a href="DesignSpecification">Design specification</a> reviewed and used in <a href="/wiki#Main-Features">Main Features</a>.<br />
+NIKHEF will start designing in June. First prototypes expected by December 2018.</td>
+</tr>
 </tbody>
 </table>
 
 -----
 
-25 May 2018
+28 May 2018