| ... | @@ -45,7 +45,11 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
... | @@ -45,7 +45,11 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- FMC slot with high pin count (HPC) connector
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- FMC slot with high pin count (HPC) connector
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- ***Under discussion. Possibly only GTX lines connected and Vadj
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- ***Under discussion. Possibly only GTX lines connected and Vadj
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fixed at 2.5V (23/10/18)***
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fixed at 2.5V (23/10/18)***
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- Vadj programmable at 1.8V and 2.5V
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- Vadj programmable at 1.8V and 2.5V.
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- \_\*Not possible due to LVDS level restrictions on the
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7-series io banks, as can be read on page 91 of the
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[manual](https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf#page=91/).
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- 2.5V can only be used with a LPC FMC mezzanine: only the LPC
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- 2.5V can only be used with a LPC FMC mezzanine: only the LPC
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pins (LA bank) are 2.5V tolerant.
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pins (LA bank) are 2.5V tolerant.
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- Fully populated LA bank
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- Fully populated LA bank
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