| ... | @@ -31,6 +31,7 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
... | @@ -31,6 +31,7 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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- *Expected cost twice of SPEC*
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- *Expected cost twice of SPEC*
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- 4-lane PCIe
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- 4-lane PCIe
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- 1x Xilinx handling PCIe interface and user gateware
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- 1x Xilinx handling PCIe interface and user gateware
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- Xilinx Kintex-7: XC7K160T in FBG676 package
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- FMC slot with high pin count (HPC) connector
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- FMC slot with high pin count (HPC) connector
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- Not full HPC connectivity (not all high-speed serial lines)
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- Not full HPC connectivity (not all high-speed serial lines)
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- Vadj adjustable **
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- Vadj adjustable **
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| ... | @@ -123,5 +124,5 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
... | @@ -123,5 +124,5 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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-----
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-----
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12 January 2018
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15 January 2018
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