| ... | ... | @@ -44,7 +44,8 @@ board*](https://www.ohwr.org/project/spec/wiki). Click the picture for a detaile |
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Table 91)
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- FMC slot with high pin count (HPC) connector
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- Fully populated LA bank
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- All 34 differential pairs connected, 2 clock pairs, JTAG, I2C (as on SPEC)
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- All 34 differential pairs connected, 2 clock pairs, I2C (as on SPEC)
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- JTAG accessible from the FPGA. JTAG switches automatically to the download cable when it is plugged.
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- Z035 and Z045 support 4 GTX transceivers DP[3:0]\_M2C/C2M
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- Vadj fixed 2.5V (HR bank of the ZYNQ only allows LVDS_25 at VCCO 2V5, see [UG471](https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf) table 1-43)
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- Clocking resources
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| ... | ... | @@ -199,4 +200,4 @@ board*](https://www.ohwr.org/project/spec/wiki). Click the picture for a detaile |
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-----
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20 January 2020 |
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24 January 2020 |
