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# Simple PCIe FMC carrier 7 (SPEC7)
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## Project description
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The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an
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SFP connector. This board is optimised for cost and is usable with most
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of the FMC cards designed within the OHR project (e.g. ADC cards, Fine
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Delay).
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The SPEC7 is the follow-up of the
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[SPEC](https://www.ohwr.org/project/spec/wiki) of which the design
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started in 2010 and for which certain components are obsolete.
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Boards with a very similar architecture are available for the VME bus
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([SVEC - Simple VME FMC Carrier
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(SVEC)](https://www.ohwr.org/project/svec/wiki)) and for the PXI
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Express bus ([SPEXI - Simple PXI express FMC Carrier Board
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(SPEXI)](https://www.ohwr.org/project/spexi/wiki)).
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Other FMC projects and the FMC standard are described in [FMC
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Projects](https://www.ohwr.org/project/fmc-projects).
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## Main Features - UNDER DISCUSSION - STILL THE OLD SPEC ONES BELOW
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- 4-lane PCIe (Gennum GN4124) *obsolete component, not available
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anymore*
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- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C) (PCI Device ID: 0x18D)
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- special versions with XC6SLX100T and XC6SLX150T available
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- FMC slot with low pin count (LPC) connector
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- Vadj fixed to 2.5V
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- FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG, I2C
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- No dedicated clock signals from Carrier to FMC (only available
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on HPC pins)
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- Clocking resources
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- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
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MHz (Silicon Labs Si570, freely usable)
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- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
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- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
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- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed
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configuration, Fout=125 MHz, used by [White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
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- On board memory
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- 1x 2Gbit (256 MByte) DDR3 (MT41J128M16HA-15E)
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- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup
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configuration, storage of the FPGA firmware or of critical data
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(M25P32-VMF6P - [EOL](https://www.ohwr.org/work_packages/1538))
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- Miscellaneous
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- on-board thermometer IC (DS18B20U+)
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- unique 64-bit identifier (DS18B20U+)
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- Front panel containing
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- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic
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transceiver
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([WhiteRabbit](https://www.ohwr.org/project/white-rabbit)
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support). 1.25 and 2.5 Gbps.
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- Programmable Red and Green LEDs
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- FMC front panel
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- Internal connectors
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- 1x JTAG header for Xilinx programming during debugging
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- 2x SATA connector
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- 1x mini USB AB (USB-UART bridge)
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- FPGA configuration. The FPGA can optionally be programmed from:
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- GN4124 SPRIO interface (loaded by software driver at startup)
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- JTAG header
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- SPI 32Mbit flash PROM
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- selectable by GN4124 GPIO. Default option would be loading via
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the SPI flash PROM (stand-alone applications).
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- Stand-alone features
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- External 12V power supply connector
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- mini USB connector
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- 4 LEDs
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- 2 buttons
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- Power consumption: 5-12 Watt, depending on application
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- Optimised for cost
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- 6-layer PCB
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- Optional cooling [fan](Fan-Design) for the mezzanine.
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-----
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## Project information
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- Official production documentation
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- [Users](Users)
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- [Frequently Asked Questions](FAQ)
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-----
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## Releases
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-----
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## Contacts
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### Commercial producers
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### General questions about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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-----
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## Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>10-01-2018</td>
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<td>Start working on project. Collecting main specifications.</td>
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</tr>
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</tbody>
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</table>
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-----
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11 January 2018
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