| ... | ... | @@ -2,7 +2,7 @@ |
|
|
|
|
|
|
|
## Project description
|
|
|
|
|
|
|
|
*The FMC PCIe Carrier called SPEC7 is an FMC carrier that can hold one
|
|
|
|
**The FMC PCIe Carrier called SPEC7 is an FMC carrier that can hold one
|
|
|
|
FMC card and an SFP connector.**
|
|
|
|
This board is optimised for low jitter and cost and is usable with most
|
|
|
|
of the FMC cards designed within the OHR project (e.g. ADC cards, Fine
|
| ... | ... | @@ -23,7 +23,7 @@ Other FMC projects and the FMC standard are described in [FMC |
|
|
|
Projects](https://www.ohwr.org/project/fmc-projects).
|
|
|
|
|
|
|
|
|
|
|
|
*The SPEC7 will be a follow-up of the [*SPEC
|
|
|
|
**The SPEC7 will be a follow-up of the [*SPEC
|
|
|
|
board*](https://www.ohwr.org/project/spec/wiki) (shown)**
|
|
|
|
|
|
|
|
-----
|
| ... | ... | @@ -50,7 +50,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
|
|
|
- ***Under discussion. Possibly only GTX lines connected and Vadj
|
|
|
|
fixed at 2.5V (23/10/18)***
|
|
|
|
- Vadj <s>programmable at 1.8V and</s> 2.5V.
|
|
|
|
- \*1.8V not possible due to LVDS level restrictions on the
|
|
|
|
- *1.8V not possible due to LVDS level restrictions on the
|
|
|
|
7-series HR-IO banks, as can be read on page 91 of the
|
|
|
|
[manual](https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf#page=91/.)*
|
|
|
|
- 2.5V can only be used with a LPC FMC mezzanine: only the LPC
|
| ... | ... | @@ -68,7 +68,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
|
|
|
(APU) (frequency?)
|
|
|
|
- 1x 10-280 MHz VCXO controlled by I2C and a DAC with SPI
|
|
|
|
interface. Starts up at 100 MHz (Silicon Labs <s>Si571</s>
|
|
|
|
***Si570 (23/10/18)***, freely usable)
|
|
|
|
**Si570 (23/10/18)**, freely usable)
|
|
|
|
- 1x 125 MHz TCXO controlled by a DAC with SPI interface (used by
|
|
|
|
[White Rabbit PTP
|
|
|
|
core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
|
| ... | ... | |
