| ... | ... | @@ -59,13 +59,14 @@ board*](https://www.ohwr.org/project/spec/wiki). Click the picture for a detaile |
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by [White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
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(Abracon ABLANO or Crystek CVPD-922 model)
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- Low jitter external 10MHz via AD9516 (supporting mode Grand Master & AbsCal)
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- Low jitter external 10MHz via LTC6950 (supporting mode Grand Master & AbsCal)
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- 10MHz TCXO for IEEE1588 v2.1 compliance (see J5.6.1) in Free-running Master mode.
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- On board memory
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- 1x 8 Gbit (1 GByte) DDR3 connected to the 32-bit wide Memory Interface
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(main use for the APU)
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- 1x 8 Gbit (1 GByte) DDR3 connected to the programmable logic (32 bit wide)
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- 1x QSPI 256 Mbit flash PROM for multiboot FPGA powerup
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configuration, storage of the FPGA firmware
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- 2x QSPI 256 Mbit flash PROM for multiboot FPGA powerup
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configuration, storage of the FPGA firmware. Note that 8-bit Dual Quad SPI is needed to meet the 100 ms PCIe endpoint requirement w.r.t. configuration time.
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- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing
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serial number, calibration parameters and other critical data
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such as the MAC address of the card
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| ... | ... | @@ -93,7 +94,7 @@ board*](https://www.ohwr.org/project/spec/wiki). Click the picture for a detaile |
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- Ethernet RJ45 connector, magnetics and MicroChip KSZ9031RNX, 10/100/1000 Mbps PHY (interface to ARM GigE)
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- Samtec Bulls-Eye connector ([BDRA: 20 signals on the PCB](https://www.samtec.com/products/bdra), 1.3 x 5.0 = 6.5 cm2 land pattern, user mountable connector)
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- ESD protection on all signals
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- 10 differential signals:
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- 11 differential signals:
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- 125 MHz reference clock in (Z035/Z045 only)
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- 125 MHz reference clock out
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- 1x tx-abscal
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| ... | ... | @@ -101,10 +102,13 @@ board*](https://www.ohwr.org/project/spec/wiki). Click the picture for a detaile |
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- PPS in/out
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- 1x GTX Tx/Rx (using 125 MHz reference clock; optional other reference clock when using Z035/Z045)
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- 1x spare
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- 124.992 MHZ DMTD clock (only for debugging purposes)
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- 1 single ended signal:
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- PPS in
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- 2x connector for optional cooling fans
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- FPGA configuration. The FPGA can optionally be programmed from:
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- JTAG header
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- QSPI 256 Mbit FLASH PROM
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- Dual QSPI 256 Mbit FLASH PROM
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- User FPGA logic: via PCIe or ARM (i.e. using [PS PCAP / ICA](see chapter 6.1.8 [Zynq-7000 SoC Technical Reference Manual](https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf))
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- Stand-alone features
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- External 12V 150W-ATX power supply connector
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| ... | ... | @@ -146,6 +150,7 @@ board*](https://www.ohwr.org/project/spec/wiki). Click the picture for a detaile |
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- Work partially funded by the EU EMPIR [WRITE
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project](http://empir.npl.co.uk/write/)
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- [Frequently Asked Questions](FAQ)
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- [Older versions](Older_versions)
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-----
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| ... | ... | @@ -189,7 +194,9 @@ board*](https://www.ohwr.org/project/spec/wiki). Click the picture for a detaile |
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| 15-08-2019 | Layout finished. |
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| 19-08-2019 | Planning: 2 boards production & assembly ready: Nov.2019. 10 boards production & assembly ready: Jan.2020
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| 18-11-2019 | First two prototypes arrived.
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| 10-12-2019 | Testing revealed a couple of minor issues and one major issue. A 2nd version PCB is needed.
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| 20-01-2020 | Layout of V2 nears is finalized.
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-----
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20 November 2019 |
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20 January 2020 |
