Peter Jansweijer · 6cbfa3f8
--- a/Home.md
+++ b/Home.md
@@ -38,65 +38,71 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
      - [XC7Z030-1FBG676C](https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf)
        (-1= slowest, commercial temp range, fast enough for most
        applications) 
-          - 4 GTX receivers (2 used for PCIe, 1 for SFP, 1 for FMC -
+          - 4 GTX receivers (2 used for PCIe, 1 for SFP, **1 external accessible**<s>, 1 for FMC - same as on SPEC</s>) 
-            same as on SPEC) 
+          - **2 GTX Reference Clocks (1 for PCIe, 1 for WR Clock)**
+          - **Note: FMC Multi Gigabit Tranceiver usage not supported for Z030 due to lack of GTX Reference Clocks**
      - Possibility to mount Z035: XC7Z035-1FBG676C or XC7Z045-1FBG676C
-          - 8 GTX receivers (2 used for PCIe, 1 for SFP, 5 for FMC)
+          - 8 GTX receivers (2 used for PCIe, 1 for SFP, **1 external accessible, 4**<s>5</s> for FMC)
+          - **4 GTX Reference Clocks (1 for PCIe, 1 for WR Clock, 1 for FMC, 1 external accessible)**
          - FBG676 6.6 Gb/s (-1 speedgrade), FFG676 10.3125 Gb/s (-2
            speedgrade) 12.5 Gb/s (-3 speedgrade) GTX transceivers
            ([DS191](https://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf),
            Table 91)
  - FMC slot with high pin count (HPC) connector
-      - ***Under discussion. Possibly only GTX lines connected and Vadj
+      - Fully populated LA bank
-        fixed at 2.5V (23/10/18)***
+          - All 34 differential pairs connected<s>, 1 GTP transceiver with
-      - Vadj <s>programmable at 1.8V and</s> 2.5V.
+            clock</s>, 2 clock pairs, JTAG, I2C (as on SPEC)
-          - *1.8V not possible due to LVDS level restrictions on the
+          - **Z035 and Z045 support 4 GTX transceivers DP[3:0]\_M2C/C2M**
+      - <s>Under discussion. Possibly only GTX lines connected and Vadj
+        fixed at 2.5V (23/10/18)</s>
+      - **Vadj fixed 2.5V (HR bank of the ZYNQ only allows LVDS_25 at VCCO 2V5, see UG471 table 1-43)**
+          -<s> *1.8V not possible due to LVDS level restrictions on the
            7-series HR-IO banks, as can be read on page 91 of the
            [manual](https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf#page=91/.)*
          - 2.5V can only be used with a LPC FMC mezzanine: only the LPC
-            pins (LA bank) are 2.5V tolerant.
+            pins (LA bank) are 2.5V tolerant.</s>
-      - Fully populated LA bank
+      - <s>Limited, partial connectivity of HPC part, 1.8V tolerant only
-          - All 34 differential pairs connected, 1 GTP transceiver with
-            clock, 2 clock pairs, JTAG, I2C (as on SPEC)
-      - Limited, partial connectivity of HPC part, 1.8V tolerant only
          - **xx** signals on HA bank
          - HA bank only 1.8V tolerant (Vadj set to 1.8V)
          - only when Xilinx Z035 or Z045 is mounted, the DP1\_M2C/C2M
-            and DP2\_M2C/2CM are connected to two GTX transceivers 
+            and DP2\_M2C/2CM are connected to two GTX transceivers </s>
  - Clocking resources
-      - 1x Fixed frequency oscillator for Application processor unit
+      - 1x Fixed frequency **33.33 MHz** oscillator for Application processor unit
-        (APU) (frequency?)
+        (APU),<s> (frequency?)</s>
      - 1x 10-280 MHz VCXO controlled by I2C and a DAC with SPI
-        interface. Starts up at 100 MHz (Silicon Labs <s>Si571</s>
+        interface. Starts up at <s>100</s>**125** MHz (Silicon Labs **Si570/Si571**, freely usable)
-        **Si570 (23/10/18)**, freely usable)
+      - 1x 125.000 MHz VCXO controlled by a DAC with SPI interface (used by
-      - 1x 125 MHz TCXO controlled by a DAC with SPI interface (used by
        [White Rabbit PTP
        core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
-        (Crystek CVPD-922 model)
+        (Crystek CVPD-922 **or Abracon ABLANO** model)
      - 1x 124.992 MHz VCXO controlled by a DAC with SPI interface (used
        by [White Rabbit PTP
        core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
-        (Crystek CVPD-922 model)
+        (Crystek CVPD-922 **or Abracon ABLANO** model)
+      - **Low jitter external 10MHz via AD9516 (supporting mode Grand Master & AbsCal)**
  - On board memory
-      - 1x 8 Gbit (1 GByte) DDR3 IC connected to the Memory Interface
+      - 1x 8 Gbit (1 GByte) DDR3 <s>IC</s> connected to the **32-bit wide** Memory Interface
        (main use for the APU)
-          - a 4 GByte SO-DIMM module cannot be used: has 64-bit
+          <s>- a 4 GByte SO-DIMM module cannot be used: has 64-bit
            interface, while the FGPA can only handle 32-bits and1 GByte
-            max)
+            max)</s>
-      - 1x 8 Gbit (1 GByte) DDR3 IC connected to the programmable logic
+      - 1x 8 Gbit (1 GByte) DDR3 <s>IC</s> connected to the programmable logic **(32 bit wide)**
-          - for bandwidth reasons
+          - <s>for bandwidth reasons
          - possibly a second 8 Gbit DDR3 IC to prevent the DDR3 problem
            of the latency and turnaround from READ to WRITE – two banks
-            solve the problem. 
+            solve the problem. </s>
-      - 1x SPI **xx** Mbit flash PROM for multiboot FPGA powerup
+      - 1x **Q**SPI **256** Mbit flash PROM for multiboot FPGA powerup
        configuration, storage of the FPGA firmware
      - 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing
        serial number, calibration parameters and other critical data
        such as the MAC address of the card
-      - 64 MB static memory (needed for booting?) 
+      - **2x 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48**
+          - **1 for APU MAC address**
+          - **1 for WR MAC address**
+      - <s>64 MB static memory (needed for booting?) </s>
      - MicroSD slot for flash memory for storing programs 
  - Miscellaneous
-      - Thermometer and semi-unique ID provided by the FPGA)
+      - Thermometer **(XADC)** and semi-unique ID **(DNA_PORTE2)** provided by the FPGA
  - Front panel containing
      - 1x Small Formfactor Pluggable+ (SFP+) cage for fibre-optic
        transceiver
@@ -106,39 +112,46 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
      - FMC front panel
  - Internal connectors
      - 1x JTAG header for Xilinx programming during debugging
-      - 1x USB-C connector
+      - 1x <s>USB-C</s>**mini USB Type B** connector
          - Can serve two UARTs over the same single mini-USB connector
            with CP2105 - Dual UART bridge IC
              - One to UART interface of the ARM, one to user logic
                (e.g., PTP core)
-      - 1x USB-C connector connected to USB port of the ARM
+      - 1x <s>USB-C</s> **USB Type A** connector connected to USB **2.0** port of the ARM
-      - Samtec Bulls-Eye connector ([22 signals on the
+      - Samtec Bulls-Eye connector ([BDRA: 20 signals on the PCB](https://www.samtec.com/products/bdra), **1.3 x 5.0 = 6.5 cm2** land pattern, user mountable connector) ** or ** ([BARA: 22 signals on the PCB](https://www.samtec.com/products/bara), **1.8 x 2.1 = 4 cm2 land pattern, user mountable connector); BDRA probably better supported but slightly bigger, final choise BDRA/BARA will depend on PCB layout**
-        PCB](https://www.samtec.com/products/bara), 6 cm2 land pattern,
-        user mountable connector)
-          - For PPS in/out, 10MHz in, tx-abscal, refclock. 5 signals to
-            be transferred in a differential way
          - ESD protection on all signals
-      - Ethernet RJ45 connector + magnetics and PHY (interface to ARM
+          - **10 differential signals:**
-        GigE)
+             - **125 MHz reference clock in/out**
+             - **1x tx-abscal**
+             - **10 MHz reference clock in/out**
+             - **PPS in/out**
+             - **1x GTX Tx/Rx**
+             - **1x spare**
+      - Ethernet RJ45 connector + magnetics and **MicroChip KSZ9031RNX, 10/100/1000 Mbps** PHY (interface to ARM GigE)
  - 1x connector for optional cooling fan
  - FPGA configuration. The FPGA can optionally be programmed from:
      - JTAG header
-      - SPI **xx** Mbit FLASH PROM
+      - **Q**SPI **256** Mbit FLASH PROM
-      - User FPGA logic: via PCIe or ARM (i.e. using [Internal
+      - User FPGA logic: via PCIe or ARM (i.e. using <s>[Internal Configuration Access Port:
-        Configuration Access Port:
+        ICAPE2](https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf)</s>
-        ICAPE2](https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf))
+        [PS PCAP / ICA](see chapter 6.1.8 https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf))
  - Stand-alone features
-      - External 12V power supply connector
+      - External 12V **150W-ATX** power supply connector
-      - USB-C connector
+      - **USB Type A** connector
-      - Ethernet
+      - <s>USB-C</s>**mini USB Type B** connector
-      - 4x LEDs
+      - **10/100/1000 Mbps** Ethernet
-      - 2x buttons
+      - <s>4</s>**6**x LEDs **(2x front pannel, 4x on PCB)**
-          - 1 connected to reset controller
+      - <s>2</s>**4**x buttons
+          - 1 **PS_POR** connected to reset controller
+          - **1 PS_SRTS_B**
          - 1 general purpose
-  - Power consumption: 5-12 Watt, depending on application
+          - **1 PROGram button for FPGA**
-  - Optimised for cost
+  - Power consumption: <s>5-12</s>**10-35** Watt, depending on application
+  - Optimized for cost
      - 8-layer PCB 
-  - Optional cooling fan for the mezzanine
+  - Optional cooling fan**s**
+     - for the mezzanine 
+     - **for the FPGA**
 -----
@@ -198,9 +211,10 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
 | 30-01-2019| Planned to have schematics ready for review on 15-Feb-19. Layout should start beginning of March.| 
 | 14-02-2019 | Schematics ready to be reviewed. |
 | 14-03-2019 | Schematics reviewed by Sundance and CERN. |
+| 29-03-2019 | Updated specifications after schematics review. |
 -----
-14 March 2019
+29 March 2019