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@@ -24,11 +24,12 @@ Projects](https://www.ohwr.org/project/fmc-projects).
 
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-  - Optmised for performance 
+  - Optimised for performance or cost?
       - High-pin count FMC, better oscillators, lower jitter, more PCB
-        layers, larger FPGA than those on SPEC
+        layers, larger FPGA than those on SPEC?
       - *SPEC was optimised for simplicity and cost*
-      - *Expected cost twice of SPEC*
+      - *If go for performance, the expected cost will be twice or three
+        times of SPEC*
   - 4-lane PCIe
   - 1x Xilinx handling PCIe interface and user gateware
       - Xilinx Kintex-7: XC7K160T in FBG676 package (XC7K160T-2FBG676C)