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- Optmised for performance
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- Optimised for performance or cost?
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- High-pin count FMC, better oscillators, lower jitter, more PCB
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layers, larger FPGA than those on SPEC
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layers, larger FPGA than those on SPEC?
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- *SPEC was optimised for simplicity and cost*
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- *Expected cost twice of SPEC*
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- *If go for performance, the expected cost will be twice or three
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times of SPEC*
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- 4-lane PCIe
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- 1x Xilinx handling PCIe interface and user gateware
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- Xilinx Kintex-7: XC7K160T in FBG676 package (XC7K160T-2FBG676C)
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