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@@ -110,14 +110,15 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
               - One to user logic (e.g., PTP core)
       - 1x <s>USB-C</s> **USB Type A** connector connected to USB **2.0** port of the ARM
       - Ethernet RJ45 connector + magnetics and **MicroChip KSZ9031RNX, 10/100/1000 Mbps** PHY (interface to ARM GigE)
-      - Samtec Bulls-Eye connector ([BDRA: 20 signals on the PCB](https://www.samtec.com/products/bdra), **1.3 x 5.0 = 6.5 cm2** land pattern, user mountable connector) **or** ([BARA: 22 signals on the PCB](https://www.samtec.com/products/bara), **1.8 x 2.1 = 4 cm2 land pattern, user mountable connector); BDRA probably better supported but slightly bigger, final choise BDRA/BARA will depend on PCB layout**
+      - Samtec Bulls-Eye connector ([BDRA: 20 signals on the PCB](https://www.samtec.com/products/bdra), **1.3 x 5.0 = 6.5 cm2** land pattern, user mountable connector)<s> **or** ([BARA: 22 signals on the PCB](https://www.samtec.com/products/bara), **1.8 x 2.1 = 4 cm2 land pattern, user mountable connector); BDRA probably better supported but slightly bigger, final choise BDRA/BARA will depend on PCB layout**</s>
           - ESD protection on all signals
           - **10 differential signals:**
-             - **125 MHz reference clock in/out**
+             - **125 MHz reference clock in (Z035/Z045 only)**
+             - **125 MHz reference clock out**
              - **1x tx-abscal**
              - **10 MHz reference clock in/out**
              - **PPS in/out**
-             - **1x GTX Tx/Rx**
+             - **1x GTX Tx/Rx (using 125 MHz reference clock; optional other when using Z035/Z045)**
              - **1x spare**
   - 1x connector for optional cooling fan
   - FPGA configuration. The FPGA can optionally be programmed from: