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@@ -18,35 +18,36 @@ Express bus ([SPEXI - Simple PXI express FMC Carrier Board
 Other FMC projects and the FMC standard are described in [FMC
 Projects](https://www.ohwr.org/project/fmc-projects).
 
-## Main Features - UNDER DISCUSSION - STILL THE OLD SPEC ONES BELOW
-
-  - 4-lane PCIe (Gennum GN4124) *obsolete component, not available
-    anymore*
-  - 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C) (PCI Device ID: 0x18D)
-      - special versions with XC6SLX100T and XC6SLX150T available
-  - FMC slot with low pin count (LPC) connector
-      - Vadj fixed to 2.5V
-      - FMC connectivity: all 34 differential pairs connected, 1 GTP
-        transceiver with clock, 2 clock pairs, JTAG, I2C
-      - No dedicated clock signals from Carrier to FMC (only available
-        on HPC pins)
+## Main Features - *Under discussion*
+
+  - Optmised for performance 
+      - High-pin count FMC, better oscillators, lower jitter, more PCB
+        layers, larger FPGA than those on SPEC
+      - *SPEC was optimised for simplicity and cost*
+      - *Expected cost twice of SPEC*
+  - 4-lane PCIe
+  - 1x Xilinx handling PCIe interface and user gateware
+  - FMC slot with high pin count (HPC) connector
+      - Not full HPC connectivity (not all high-speed serial lines)
+      - Vadj adjustable **
+      - Dedicated clock signals from Carrier to FMC (available on HPC
+        pins) ?
   - Clocking resources
       - 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
         MHz (Silicon Labs Si570, freely usable)
-      - 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
-        used by [White Rabbit PTP
+      - 1x 25 MHz TCXO with adjustable frequency (<s>AD5662</s>, used by
+        [White Rabbit PTP
         core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
-      - 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
-        used by [White Rabbit PTP
+      - 1x 20 MHz VCXO with adjustable frequency (<s>AD5662</s>, used by
+        [White Rabbit PTP
         core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
-      - 1x low-jitter frequency synthesizer (TI CDCM61004, fixed
+      - 1x low-jitter frequency synthesizer (<s>TI CDCM61004</s>, fixed
         configuration, Fout=125 MHz, used by [White Rabbit PTP
         core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
   - On board memory
-      - 1x 2Gbit (256 MByte) DDR3 (MT41J128M16HA-15E)
-      - 1x SPI 32Mbit flash PROM for multiboot FPGA powerup
-        configuration, storage of the FPGA firmware or of critical data
-        (M25P32-VMF6P - [EOL](https://www.ohwr.org/work_packages/1538))
+      - 1x 2Gbit (256 MByte) DDR3 (?)
+      - 1x SPI flash PROM for multiboot FPGA powerup configuration,
+        storage of the FPGA firmware or of critical data
   - Miscellaneous
       - on-board thermometer IC (DS18B20U+)
       - unique 64-bit identifier (DS18B20U+)
@@ -62,21 +63,21 @@ Projects](https://www.ohwr.org/project/fmc-projects).
       - 2x SATA connector 
       - 1x mini USB AB (USB-UART bridge)
   - FPGA configuration. The FPGA can optionally be programmed from:
-      - GN4124 SPRIO interface (loaded by software driver at startup)
       - JTAG header
       - SPI 32Mbit flash PROM
-      - selectable by GN4124 GPIO. Default option would be loading via
-        the SPI flash PROM (stand-alone applications).
+      - Partial reprogramming via PCIe
   - Stand-alone features
       - External 12V power supply connector
       - mini USB connector
       - 4 LEDs
       - 2 buttons
   - Power consumption: 5-12 Watt, depending on application
-  - Optimised for cost
-      - 6-layer PCB
   - Optional cooling [fan](Fan-Design) for the mezzanine.
 
+<!-- end list -->
+
+  - \[specgather|Specification gathering discussion\]
+
 -----
 
 ## Project information