| ... | @@ -61,7 +61,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
... | @@ -61,7 +61,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
|
|
- Limited, partial connectivity of HPC part, 1.8V tolerant only
|
|
- Limited, partial connectivity of HPC part, 1.8V tolerant only
|
|
|
- **xx** signals on HA bank
|
|
- **xx** signals on HA bank
|
|
|
- HA bank only 1.8V tolerant (Vadj set to 1.8V)
|
|
- HA bank only 1.8V tolerant (Vadj set to 1.8V)
|
|
|
- only when Xilinx Z035 or Z040 is mounted, the DP1\_M2C/C2M
|
|
- only when Xilinx Z035 or Z045 is mounted, the DP1\_M2C/C2M
|
|
|
and DP2\_M2C/2CM are connected to two GTX transceivers
|
|
and DP2\_M2C/2CM are connected to two GTX transceivers
|
|
|
- Clocking resources
|
|
- Clocking resources
|
|
|
- 1x Fixed frequency oscillator for Application processor unit
|
|
- 1x Fixed frequency oscillator for Application processor unit
|
| ... | | ... | |
