Home.md

@@ -43,6 +43,8 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
       - Possibility to mount Z035: XC7Z035-1FBG676C or XC7Z045-1FBG676C
           - 8 GTX receivers (2 used for PCIe, 1 for SFP, 5 for FMC)
   - FMC slot with high pin count (HPC) connector
+      - ***Under discussion. Possibly only GTX lines connected and Vadj
+        fixed at 2.5V (23/10/18)***
       - Vadj programmable at 1.8V and 2.5V
           - 2.5V can only be used with a LPC FMC mezzanine: only the LPC
             pins (LA bank) are 2.5V tolerant.
@@ -58,8 +60,8 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
       - 1x Fixed frequency oscillator for Application processor unit
         (APU) (frequency?)
       - 1x 10-280 MHz VCXO controlled by I2C and a DAC with SPI
-        interface. Starts up at 100 MHz (Silicon Labs Si571, freely
-        usable)
+        interface. Starts up at 100 MHz (Silicon Labs <s>Si571</s>
+        ***Si570 (23/10/18)***, freely usable)
       - 1x 125 MHz TCXO controlled by a DAC with SPI interface (used by
         [White Rabbit PTP
         core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
@@ -223,5 +225,5 @@ Prototype available by end April 2019.</td>
 
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-17 September 2018
+23 October 2018