| ... | @@ -33,7 +33,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
... | @@ -33,7 +33,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- 2-lane PCIe Gen2
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- 2-lane PCIe Gen2
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- Same 1 GByte/s total speed as 4-lane PCIe Gen1 on SPEC. Bridge
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- Same 1 GByte/s total speed as 4-lane PCIe Gen1 on SPEC. Bridge
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integrated in FPGA
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integrated in FPGA
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- Xilinx Zynq FPGA with ARM processor
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- Xilinx Zynq FPGA with Dual-Core ARM processor
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integrated
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integrated
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- [XC7Z030-1FBG676C](https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf)
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- [XC7Z030-1FBG676C](https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf)
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(-1= slowest, commercial temp range, fast enough for most
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(-1= slowest, commercial temp range, fast enough for most
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| ... | @@ -225,5 +225,5 @@ Prototype available by end April 2019.</td> |
... | @@ -225,5 +225,5 @@ Prototype available by end April 2019.</td> |
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-----
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-----
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23 October 2018
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24 October 2018
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