| ... | ... | @@ -76,6 +76,9 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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max)
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- 1x 8 Gbit (1 GByte) DDR3 IC connected to the programmable logic
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- for bandwidth reasons
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- Possibly a second 8 Gbit DDR3 IC to prevent the DDR3 problem
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of the latency and turnaround from READ to WRITE – two banks
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solve the problem.
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- 1x SPI **xx** Mbit flash PROM for multiboot FPGA powerup
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configuration, storage of the FPGA firmware
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- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing
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| ... | ... | @@ -205,5 +208,5 @@ NIKHEF will start designing in June. First prototypes expected by December 2018. |
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-----
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28 May 2018
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30 May 2018
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