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- Same 1 GByte/s total speed as 4-lane PCIe Gen1 on SPEC. Bridge
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integrated in FPGA
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- Xilinx Zynq FPGA with Dual-Core ARM processor integrated
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- [XC7Z030-1FBG676C](https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf)
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(-1= slowest, commercial temp range, fast enough for most
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- [XC7Z035-1FBG676C](https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf) (-1= slowest, commercial temp range, fast enough for most
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applications)
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- 4 GTX Tranceivers (2 used for PCIe, 1 for SFP, 1 external accessible)
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- 2 GTX Reference Clocks (1 for PCIe, 1 for WR Clock)
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- Note: FMC Multi Gigabit Tranceiver usage not supported for Z030 due to lack of GTX Reference Clocks
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- Possibility to mount Z035: XC7Z035-1FBG676C or XC7Z045-1FBG676C
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- 8 GTX Tranceivers (2 used for PCIe, 1 for SFP, 1 external accessible, 4 for FMC)
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- 4 GTX Reference Clocks (1 for PCIe, 1 for WR Clock, 1 for FMC, 1 external accessible)
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- FBG676 6.6 Gb/s (-1 speedgrade), FFG676 10.3125 Gb/s (-2
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speedgrade) 12.5 Gb/s (-3 speedgrade) GTX transceivers
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([DS191](https://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf),
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Table 91)
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speedgrade) or 12.5 Gb/s (-3 speedgrade) GTX transceivers
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([DS191](https://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf), Table 91)
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- Possibility to mount XC7Z045-1FBG676C, but not XC7Z030-1FBG676C (see Issue #22)
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- FMC slot with high pin count (HPC) connector
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- Fully populated LA bank
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- All 34 differential pairs connected, 2 clock pairs, I2C (as on SPEC)
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| ... | ... | @@ -209,4 +204,4 @@ board*](https://www.ohwr.org/project/spec/wiki). Click the picture for a detaile |
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-----
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18 September 2020 |
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10 December 2020 |
