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Simple PCIe FMC carrier SPEC
Commit aa01b719 authored by Federico Vaga's avatar Federico Vaga
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sw:drv: unaligned accesses are not supported 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 54242b66
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Showing with 37 additions and 12 deletions
pytest/test_dma.py
View file @ aa01b719
......@@ -71,31 +71,53 @@ class TestDma(object):
assert count == buffer_size
spec.dma_stop()
@pytest.mark.parametrize("ddr_offset",
[2**i for i in range(2, int(math.log2(PySPEC.DDR_SIZE)))])
@pytest.mark.parametrize("unaligned", range(1, PySPEC.DDR_ALIGN))
def test_dma_unaligned_offset_read(self, spec, ddr_offset, unaligned):
"""
The DDR access is 4byte aligned.
"""
spec.dma_start()
with pytest.raises(OSError) as error:
spec.dma_read(ddr_offset + unaligned, 16)
spec.dma_stop()
@pytest.mark.parametrize("buffer_size", [1, 2, 3])
def test_dma_invalid_size_read(self, spec, buffer_size):
@pytest.mark.parametrize("ddr_offset",
[2**i for i in range(2, int(math.log2(PySPEC.DDR_SIZE)))])
@pytest.mark.parametrize("unaligned", range(1, PySPEC.DDR_ALIGN))
def test_dma_unaligned_offset_write(self, spec, ddr_offset, unaligned):
"""
The HDL engine masks the 2 least significant bits. For small transfers
this translates into a zero length transfer which is not supported.
Also 0 is an invalid size, but read/write returns immediatly because
there is nothing to transfer.
The DDR access is 4byte aligned.
"""
spec.dma_start()
with pytest.raises(OSError) as error:
spec.dma_read(0, buffer_size)
spec.dma_write(ddr_offset + unaligned, b"\x00" * 16)
spec.dma_stop()
@pytest.mark.parametrize("buffer_size", [1, 2, 3])
def test_dma_invalid_size_write(self, spec, buffer_size):
@pytest.mark.parametrize("ddr_offset",
[2**i for i in range(2, int(math.log2(PySPEC.DDR_SIZE)))])
@pytest.mark.parametrize("unaligned", range(1, PySPEC.DDR_ALIGN))
def test_dma_unaligned_size_read(self, spec, ddr_offset, unaligned):
"""
The HDL engine masks the 2 least significant bits. For small transfers
this translates into a zero length transfer which is not supported.
The DDR access is 4byte aligned.
"""
spec.dma_start()
with pytest.raises(OSError) as error:
spec.dma_write(0, b"\x00" * buffer_size)
spec.dma_read(ddr_offset + unaligned, (16 + unaligned))
spec.dma_stop()
@pytest.mark.parametrize("ddr_offset",
[2**i for i in range(2, int(math.log2(PySPEC.DDR_SIZE)))])
@pytest.mark.parametrize("unaligned", range(1, PySPEC.DDR_ALIGN))
def test_dma_unaligned_size_write(self, spec, ddr_offset, unaligned):
"""
The DDR access is 4byte aligned.
"""
spec.dma_start()
with pytest.raises(OSError) as error:
spec.dma_write(ddr_offset + unaligned, b"\x00" * (16 + unaligned))
spec.dma_stop()
@pytest.mark.parametrize("dma_offset", [0x0])
@pytest.mark.parametrize("dma_size",
......
software/kernel/spec-core-fpga.c
View file @ aa01b719
......@@ -161,6 +161,9 @@ static int spec_fpga_dbg_dma_transfer(struct spec_fpga_dbg_dma *dbgdma,
struct scatterlist *sg;
int i;
if (count & 0x3 || offset & 0x3)
return -EINVAL;
max_segment = dma_get_max_seg_size(dbgdma->dchan->device->dev) & PAGE_MASK;
err = sg_alloc_table(&sgt, (count / max_segment) + 1, GFP_KERNEL);
if (err)
......
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