spec_base_wr: forward the value of SPLL AUX Clock config generic to xwrc_board_common

5d2c61f7 · Tomasz Wlostowski · 69137122 · 5d2c61f7
Commit 5d2c61f7 authored Apr 04, 2023 by Tomasz Wlostowski
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Showing with 3 additions and 2 deletions

spec_base_wr.vhd hdl/rtl/spec_base_wr.vhd +3 -2

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--- a/hdl/rtl/spec_base_wr.vhd
+++ b/hdl/rtl/spec_base_wr.vhd
@@ -763,7 +763,7 @@ begin  -- architecture top
                   adr => wrc_out.adr or x"00020000",
                   sel => wrc_out.sel, we => wrc_out.we, dat => wrc_out.dat);

-    cmp_xwrc_board_spec : xwrc_board_spec
+    cmp_xwrc_board_spec : entity work.xwrc_board_spec
      generic map (
        g_simulation                => boolean'pos(g_SIMULATION),
        g_VERBOSE                   => g_VERBOSE,
@@ -774,7 +774,8 @@ begin  -- architecture top
        g_STREAMERS_OP_MODE         => g_STREAMERS_OP_MODE,
        g_TX_STREAMER_PARAMS        => g_TX_STREAMER_PARAMS,
        g_RX_STREAMER_PARAMS        => g_RX_STREAMER_PARAMS,
-        g_FABRIC_IFACE              => g_FABRIC_IFACE)
+        g_FABRIC_IFACE              => g_FABRIC_IFACE,
+        g_softpll_aux_channel_config => g_softpll_aux_channel_config)
      port map (
        areset_n_i          => button1_n_i,
        areset_edge_n_i     => gn_rst_n_i,