Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
S
Simple PCIe FMC carrier SPEC
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
50
Issues
50
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Simple PCIe FMC carrier SPEC
Commits
5861d188
Commit
5861d188
authored
May 19, 2020
by
Tomasz Wlostowski
Committed by
Federico Vaga
May 28, 2020
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl/spec_base_wr: tie sim_wb_i to 0s when not used
parent
8bbdf20f
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 addition
and
1 deletion
+1
-1
spec_base_wr.vhd
hdl/rtl/spec_base_wr.vhd
+1
-1
No files found.
hdl/rtl/spec_base_wr.vhd
View file @
5861d188
...
@@ -303,7 +303,7 @@ entity spec_base_wr is
...
@@ -303,7 +303,7 @@ entity spec_base_wr is
app_wb_o
:
out
t_wishbone_master_out
;
app_wb_o
:
out
t_wishbone_master_out
;
app_wb_i
:
in
t_wishbone_master_in
;
app_wb_i
:
in
t_wishbone_master_in
;
sim_wb_i
:
in
t_wishbone_slave_in
;
sim_wb_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
sim_wb_o
:
out
t_wishbone_slave_out
sim_wb_o
:
out
t_wishbone_slave_out
);
);
end
entity
spec_base_wr
;
end
entity
spec_base_wr
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment