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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
475d238d
Commit
475d238d
authored
Jul 12, 2011
by
Matthieu Cattin
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Add manifests, rename top module and synthesis dir.
parent
59b14a51
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5 changed files
with
28 additions
and
11 deletions
+28
-11
Manifest.py
hdl/test_ddr/rtl/Manifest.py
+5
-0
spec_ddr_test.vhd
hdl/test_ddr/rtl/spec_ddr_test.vhd
+3
-3
spec_ddr_test.ucf
hdl/test_ddr/spec_ddr_test.ucf
+0
-0
Manifest.py
hdl/test_ddr/syn/Manifest.py
+12
-0
spec_ddr_test.xise
hdl/test_ddr/syn/spec_ddr_test.xise
+8
-8
No files found.
hdl/test_ddr/rtl/Manifest.py
0 → 100644
View file @
475d238d
files
=
[
"spec_ddr_test_top.vhd"
,
"gpio_regs.vhd"
]
modules
=
{
"svn"
:
[
"http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl"
,
"http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl/spec/rtl"
]}
hdl/test_ddr/rtl/spec_ddr_test
_top
.vhd
→
hdl/test_ddr/rtl/spec_ddr_test.vhd
View file @
475d238d
...
...
@@ -31,7 +31,7 @@ library UNISIM;
use
UNISIM
.
vcomponents
.
all
;
entity
spec_
top
is
entity
spec_
ddr_test
is
generic
(
g_SIMULATION
:
string
:
=
"FALSE"
;
g_CALIB_SOFT_IP
:
string
:
=
"TRUE"
);
...
...
@@ -106,10 +106,10 @@ entity spec_top is
DDR3_ZIO
:
inout
std_logic
;
DDR3_RZQ
:
inout
std_logic
);
end
spec_
top
;
end
spec_
ddr_test
;
architecture
rtl
of
spec_
top
is
architecture
rtl
of
spec_
ddr_test
is
------------------------------------------------------------------------------
-- Components declaration
...
...
hdl/test_ddr/spec_
top
.ucf
→
hdl/test_ddr/spec_
ddr_test
.ucf
View file @
475d238d
File moved
hdl/test_ddr/syn/Manifest.py
0 → 100644
View file @
475d238d
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"spec_ddr_test"
syn_project
=
"spec_ddr_test.xise"
files
=
[
"../spec_ddr_test.ucf"
]
modules
=
{
"local"
:
"../rtl"
}
hdl/test_ddr/
ise_project
/spec_ddr_test.xise
→
hdl/test_ddr/
syn
/spec_ddr_test.xise
View file @
475d238d
...
...
@@ -26,19 +26,19 @@
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/
gn4124_core_pkg_s6
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/
spartan6/gn4124_core_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/
gn4124_core_s6
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/
spartan6/gn4124_core
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/
l2p_ser_s6
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/
spartan6/l2p_ser
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/
p2l_des_s6
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/
spartan6/p2l_des
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
...
...
@@ -70,19 +70,19 @@
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/s
partan6/s
erdes_n_to_1_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/s
partan6/s
erdes_n_to_1_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/s
partan6/s
erdes_1_to_n_clk_pll_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../GN4124_core/hdl/gn4124core/rtl/s
partan6/s
erdes_1_to_n_data_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
/>
<association
xil_pn:name=
"Implementation"
/>
</file>
...
...
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