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Simple PCIe FMC carrier SPEC
Commit 2fb3e785 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] add g_VERBOSE flag to template

parent e19fbccf
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Showing with 4 additions and 1 deletion
hdl/rtl/spec_template_wr.vhd
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...@@ -66,7 +66,9 @@ entity spec_template_wr is ...@@ -66,7 +66,9 @@ entity spec_template_wr is
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench. -- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations. -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0 g_SIMULATION : integer := 0;
-- Increase information messages during simulation
g_VERBOSE : boolean := False
); );
port ( port (
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -757,6 +759,7 @@ begin -- architecture top ...@@ -757,6 +759,7 @@ begin -- architecture top
cmp_xwrc_board_spec : xwrc_board_spec cmp_xwrc_board_spec : xwrc_board_spec
generic map ( generic map (
g_simulation => g_SIMULATION, g_simulation => g_SIMULATION,
g_VERBOSE => g_VERBOSE,
g_with_external_clock_input => TRUE, g_with_external_clock_input => TRUE,
g_dpram_initf => g_DPRAM_INITF, g_dpram_initf => g_DPRAM_INITF,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG, g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
......
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