... | ... | @@ -191,23 +191,19 @@ Clock missing. Supply Xilinx wrong. Cleanup required.</td> |
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<td>All ICs and most slow lines of FMC connector tested. Not yet gigabit lines.</td>
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</tr>
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<tr class="odd">
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<td>01-03-2011</td>
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<td>Planned review of "V1.1" for fast production for WR developers.</td>
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</tr>
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<tr class="even">
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<td>02-03-2011</td>
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<td>Review of "V1.1" schematics and PCB.</td>
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</tr>
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<tr class="odd">
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<tr class="even">
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<td>07-03-2011</td>
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<td>V1.1 sent out for production of 20 boards.</td>
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<td>Ordered 10 "V1.1" boards for CERN. Company will produce extra for <a href="https://www.ohwr.org/project/white-rabbit">WR</a> development.</td>
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</tr>
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</tbody>
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</table>
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-----
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Erik van der Bij, Tomasz Wlostowski - 24 February 2011
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Erik van der Bij, Tomasz Wlostowski - 25 March 2011
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... | ... | |