... | ... | @@ -17,50 +17,52 @@ Projects](https://www.ohwr.org/project/fmc-projects). |
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## Main Features
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\* 4-lane PCIe (Gennum GN4124)
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\* FMC slot with low pin count (LPC) connector
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o Vadj fixed to 2.5V
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o No dedicated clock signals from Carrier to FMC (only available on HPC
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pins)
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o LPC cheaper than HPC and also easier to mount
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o FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG
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\* 1 Xilinx Spartan6 FPGA (XC6SLX45T)
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\* Simple clocking resources
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o 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
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o 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
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o 1 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)
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o 1 low-jitter frequency synthesizer (TI CDCM61004, fixed configuration,
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Fout=125MHz)
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\* On board memory
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o A 2Gbit DDR3
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o 1 SPI 32Mbit flash PROM for multiboot FPGA powerup configuration,
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storage of the FPGA firmware or of critical data
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\* Miscellaneous
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o on-board thermometer IC (DS18B20U+)
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o unique 64-bit identifier (DS18B20U+)
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\* Front panel containing
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o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver
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([WhiteRabbit](https://www.ohwr.org/project/white-rabbit) support)
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o Programmable LED
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o FMC front panel
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\* Internal connectors
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o 1 JTAG header for Xilinx programming during debugging
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o 2 SATA connector
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o 1 mini USB AB (USB-UART bridge)
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\* FPGA configuration. The FPGA can optionally be programmed from:
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o GN4124 SPRIO interface (loaded by software driver at startup)
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o JTAG header
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o SPI 32Mbit flash PROM
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o selectable by GN4124 GPIO. Default option would be loading via the SPI
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flash PROM (stand-alone applications).
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\* Stand-alone features
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o External 12V power supply connector
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o mini USB connector
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o 4 LEDs
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o 2 buttons
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\* Optimised for cost
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o 6-layer PCB
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- 4-lane PCIe (Gennum GN4124)
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- FMC slot with low pin count (LPC) connector
|
|
|
- Vadj fixed to 2.5V
|
|
|
- FMC connectivity: all 34 differential pairs connected, 1 GTP
|
|
|
transceiver with clock, 2 clock pairs, JTAG
|
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- No dedicated clock signals from Carrier to FMC (only available
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on HPC pins)
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- 1x Xilinx Spartan6 FPGA (XC6SLX45T)
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- Simple clocking resources
|
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- 1x 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs
|
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Si570)
|
|
|
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
|
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- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)
|
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- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed
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configuration, Fout=125MHz)
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- On board memory
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- 1x 2Gbit DDR3
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- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup
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configuration, storage of the FPGA firmware or of critical data
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- Miscellaneous
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- on-board thermometer IC (DS18B20U+)
|
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- unique 64-bit identifier (DS18B20U+)
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|
|
- Front panel containing
|
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|
- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic
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transceiver
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([WhiteRabbit](https://www.ohwr.org/project/white-rabbit)
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support)
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- Programmable Red and Green LEDs
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- FMC front panel
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- Internal connectors
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- 1x JTAG header for Xilinx programming during debugging
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- 2x SATA connector
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- 1x mini USB AB (USB-UART bridge)
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- FPGA configuration. The FPGA can optionally be programmed from:
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|
- GN4124 SPRIO interface (loaded by software driver at startup)
|
|
|
- JTAG header
|
|
|
- SPI 32Mbit flash PROM
|
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- selectable by GN4124 GPIO. Default option would be loading via
|
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the SPI flash PROM (stand-alone applications).
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- Stand-alone features
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- External 12V power supply connector
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- mini USB connector
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- 4 LEDs
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- 2 buttons
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- Optimised for cost
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- 6-layer PCB
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-----
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... | ... | @@ -114,7 +116,7 @@ o 6-layer PCB |
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</tr>
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<tr class="even">
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<td>22-06-2010</td>
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<td>Start of project. Design will be done by an external company, based on the <a href="https://www.ohwr.org/project/fmc-pci-carrier">FMC PCIe Carrier</a>.<br />
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<td>Start of project. Design is done by an external company, based on the <a href="https://www.ohwr.org/project/fmc-pci-carrier">FMC PCIe Carrier</a>.<br />
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Reviewing will be done by CERN.</td>
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</tr>
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<tr class="odd">
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... | ... | @@ -126,198 +128,48 @@ Reviewing will be done by CERN.</td> |
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<td>First schematics published. Ready for review.</td>
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</tr>
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<tr class="odd">
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<td>16-07-2010</td>
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<td>First review held. Considered as a preliminary review as schematics not finished.</td>
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</tr>
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<tr class="even">
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<td>24-07-2010</td>
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<td>Second version schematics published.</td>
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</tr>
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<tr class="odd">
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<td>03-08-2010</td>
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<td>Second schematics review held. FMC to Xilinx bank connections not correct.<br />
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Clock missing. Supply Xilinx wrong. Cleanup required.</td>
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</tr>
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<tr class="even">
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<td>03-09-2010</td>
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<td>Schematics corrected. Waiting for a final schematics review from CERN.</td>
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</tr>
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<tr class="odd">
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<td>07-09-2010</td>
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<td>Third schematics review held. [review07092010](review07092010)</td>
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</tr>
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<tr class="even">
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<td>10-09-2010</td>
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<td>Review comments integrated <a href="review07092010comments" class="uri">review07092010comments</a>. Start of PCB layout.</td>
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</tr>
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<tr class="odd">
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<td>21-09-2010</td>
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<td>PCB layout being made. Will fit on a 6-layer board.</td>
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<td>Review comments integrated. Start of PCB layout.</td>
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</tr>
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<tr class="even">
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<td>27-09-2010</td>
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<td>PCB layout 'ready'.</td>
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</tr>
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<tr class="odd">
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<td>01-10-2010</td>
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<td>PCB layout modified before review.</td>
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</tr>
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<tr class="even">
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<td>04-10-2010</td>
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<td>Preliminary PCB layout review requiring modifications to layout. [review04102010](review04102010)</td>
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</tr>
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<tr class="odd">
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<td>05-10-2010</td>
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<td>PCB layout review held. [review05102010](review05102010)</td>
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</tr>
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<tr class="even">
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<td>08-10-2010</td>
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<td><a href="https://edh.cern.ch/Document/SupplyChain/DAI/4476636">Order</a> placed for production of three prototypes.</td>
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</tr>
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<tr class="odd">
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<td>18-10-2010</td>
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<td>Some final mods to the schematics and PCB. Design passses CERN's design office for standard production files.</td>
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</tr>
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<tr class="even">
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<td>19-10-2010</td>
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<td>Board could not generate interrupts. Found before finalising production files.</td>
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</tr>
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<tr class="odd">
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<td>20-10-2010</td>
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<td>Vias designed next to BGA pads which may cause production problems. Needs rework of layout.</td>
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</tr>
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<tr class="even">
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<td>29-10-2010</td>
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<td>Received improved layout. Will pass via CERN's design office.</td>
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<td>PCB layout review held.</td>
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</tr>
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<tr class="odd">
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<td>05-11-2010</td>
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<td>Design finished. Expect ordered boards by <del>mid December</del> January.</td>
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<td>Design finished.</td>
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</tr>
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<tr class="even">
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<td>20-12-2010</td>
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<td>Production of 3 prototype board finished (see photo above)</td>
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</tr>
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<tr class="odd">
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<td>19-01-2011</td>
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<td>Three prototypes arrived at CERN.</td>
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</tr>
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<tr class="even">
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<td>19-01-2011</td>
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<td>Started testing V1 [TestingV1](TestingV1)</td>
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</tr>
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<tr class="odd">
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<td>04-02-2011</td>
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<td>First DDR3 access</td>
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</tr>
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<tr class="even">
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<td>04-02-2011</td>
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<td>WhiteRabbit port GTP transceiver working. Packet Tx/Rx in progress...</td>
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</tr>
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<tr class="odd">
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<td>06-02-2011</td>
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<td>Packet transmission and reception works!</td>
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</tr>
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<tr class="even">
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<td>24-02-2011</td>
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<td>All ICs and most slow lines of FMC connector tested. Not yet gigabit lines.</td>
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</tr>
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<tr class="odd">
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<td>02-03-2011</td>
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<td>Review of "V1.1" schematics and PCB.</td>
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</tr>
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<tr class="even">
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<td>07-03-2011</td>
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<td>Ordered 10 "V1.1" boards for CERN. Company will produce extra for <a href="https://www.ohwr.org/project/white-rabbit">WR</a> development.</td>
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</tr>
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<tr class="odd">
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<td>11-04-2011</td>
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<td>Improved version of "V1.1" layout sent for verification by CERN's design office. Planned ready by 29-04-2011.</td>
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</tr>
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<tr class="even">
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<td>18-04-2011</td>
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<td>First V1.1 prototypes received, start testing them.</td>
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</tr>
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<tr class="odd">
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<td>02-05-2011</td>
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<td>V1.1 partly tested. Cleaning up schematics for production. Found missing pull-ups.</td>
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</tr>
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<tr class="even">
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<td>09-05-2011</td>
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<td>Review of updated schematics planned to be held on 11-05-2011. [review11052011](review11052011)</td>
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</tr>
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<tr class="odd">
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<td>16-05-2011</td>
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<td>Schematics, layout and production documents for V2 are available in [EDMS](https://edms.cern.ch/nav/P:EDA-02189:V0/I:EDA-02189-V2-0:V0/TAB4)</td>
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</tr>
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<tr class="even">
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<td>20-05-2011</td>
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<td>CERN sent out price enquiry for production of 70 boards. Delivery of pre-series in October.</td>
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</tr>
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<tr class="odd">
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<td>31-05-2011</td>
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<td>Sent order for 3 production prototypes. <a href="http://edh.cern.ch/Info/Order/CA/1519947">Order</a> (CERN only).<br />
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Demo of production test software shown. Needs only minor modifications.</td>
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</tr>
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<tr class="even">
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<td>16-06-2011</td>
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<td>V2 boards being built.</td>
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</tr>
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<tr class="odd">
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<td>01-07-2011</td>
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<td>Three V2 boards received. One fully tested OK. Two only shortly tested.</td>
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</tr>
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<tr class="even">
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<td>14-07-2011</td>
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<td>Modifications for V3 (OHL v1.1, 1 crossover SATA), [changelog](V3ChangeLog)</td>
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</tr>
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<tr class="odd">
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<td>17-07-2011</td>
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<td>Order placed for 70 SPEC cards at Seven Solutions. First batch expected end October.</td>
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<td>Order placed for 70 SPEC cards at Seven Solutions.</td>
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</tr>
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<tr class="even">
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<td>25-07-2011</td>
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<td>V3 released. But never built.</td>
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</tr>
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<tr class="odd">
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<td>23-08-2011</td>
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<td>V4 released. Solves a minor mechanical problem with the SFP connector.</td>
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</tr>
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<tr class="even">
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<td>21-11-2011</td>
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<td>Pre-production serie of 10 boards was not compliant to IPC-A-610 (Class 2).</td>
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</tr>
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<tr class="odd">
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<td>16-01-2012</td>
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<td>Will receive <del>8</del> 11 boards by <del>mid February</del> 7 March. (Update 24-02-2012), another 59 by end April.</td>
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</tr>
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<tr class="even">
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<td>14-03-2012</td>
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<td>CERN accepted the 10 preseries boards that were received on 7 March.</td>
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</tr>
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<tr class="odd">
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<td>26-04-2012</td>
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<td>Will receive another 27 cards from Seven Solution by mid-June. And 33 out of the order of 70 later.</td>
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</tr>
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<tr class="even">
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<td>12-06-2012</td>
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<td>SPEC boards passed most restrictive EMC tests for industrial and domestic classes. [Test report](https://www.ohwr.org/project/spec/wikis/Documents/EMC-Test-report).</td>
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</tr>
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<tr class="odd">
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<td>13-06-2012</td>
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<td>CERN ordered 60 cards at INCAA for delivery end September.</td>
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</tr>
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<tr class="even">
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<td>03-07-2012</td>
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<td>Seven Solutions delivered 52 cards. 8 to be delivered later.</td>
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</tr>
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<tr class="odd">
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<td>18-07-2012</td>
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<td>Seven Solutions delivered final 8 cards.</td>
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</tr>
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<tr class="even">
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<td>10-09-2012</td>
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<td>CERN entered the modules in the stock for later use in LHC and other accelerators.</td>
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<td>Board available from three commercial producers.</td>
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</tr>
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</tbody>
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</table>
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... | ... | @@ -326,7 +178,7 @@ Demo of production test software shown. Needs only minor modifications.</td> |
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-----
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Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 22 September 2012
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Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 5 November 2012
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... | ... | |