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Simple PCIe FMC carrier SPEC
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proposed_master
b3d2bfc2
·
spec_base_wr: automatically set the g_BANK_PORT_SELECT generic.
·
Sep 18, 2019
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tom-apr24
c95da978
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fixed DDR reset polarity
·
Apr 25, 2020
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tom-apr28
cbe5c7ee
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spec_base_wr: disable DDR3 controller g_CALIB_SOFT_IP when running a...
·
Apr 29, 2020
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Branch_v1.4.14
4c3ac537
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hdl: fixed DDR reset polarity
·
Jun 16, 2020
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feature/autotools
fc9596c2
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Adopt autotools
·
Feb 13, 2022
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feature/python3-pyspec
ee446641
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bld: build python package
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Feb 24, 2022
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adam-tdc
a7d98f10
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hdl/rtl/spec_base_regs: fix spec_base_regs.cheby for rest map generation
·
Jun 22, 2022
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prova
baed84b2
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nuovo
·
Jul 01, 2022
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varodek_develop_spec
de1742e7
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kernel: spec-core: remove legacy code
·
Nov 08, 2022
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tom-femto-st-visit-apr03
5d2c61f7
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spec_base_wr: forward the value of SPLL AUX Clock config generic to xwrc_board_common
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Apr 04, 2023
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17-update-ci-to-use-generic-edl-jobs
8d3a9bb6
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doc: reduce requirements
·
Apr 11, 2023
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master-patch-89b8
e3e92d0a
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test
·
Sep 12, 2023
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