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Commit bcbef14c authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Initial HDL design

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hdl/ip_cores/ddr_sync_fifo/Manifest.py 0 → 100644
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files = [ "ddr_sync_fifo.vhd",
"ddr_sync_fifo.ngc" ]
hdl/ip_cores/ddr_sync_fifo/coregen.cgc 0 → 100644
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hdl/ip_cores/ddr_sync_fifo/coregen.cgp 0 → 100644
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# Date: Wed Jun 05 13:00:42 2013
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: e7f77b83
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo.asy 0 → 100644
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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 ddr_sync_fifo
RECTANGLE Normal 32 32 800 4064
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName rst
PINATTR Polarity IN
LINE Normal 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wr_clk
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din[17:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName wr_en
PINATTR Polarity IN
LINE Normal 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName full
PINATTR Polarity OUT
LINE Normal 832 240 800 240
PIN 832 240 RIGHT 36
PINATTR PinName rd_clk
PINATTR Polarity IN
LINE Wide 832 272 800 272
PIN 832 272 RIGHT 36
PINATTR PinName dout[35:0]
PINATTR Polarity OUT
LINE Normal 832 304 800 304
PIN 832 304 RIGHT 36
PINATTR PinName rd_en
PINATTR Polarity IN
LINE Normal 832 496 800 496
PIN 832 496 RIGHT 36
PINATTR PinName empty
PINATTR Polarity OUT
LINE Wide 832 656 800 656
PIN 832 656 RIGHT 36
PINATTR PinName rd_data_count[5:0]
PINATTR Polarity OUT
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo.gise 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ddr_sync_fifo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="ddr_sync_fifo.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ddr_sync_fifo.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo.ngc 0 → 100644
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hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo.vhd 0 → 100644
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hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo.vho 0 → 100644
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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --
-- --
-- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --
-- memory queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
--------------------------------------------------------------------------------
-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
-- master_aclk
-- slave_aclk
-- slave_aresetn
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT ddr_sync_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ddr_sync_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
rd_data_count => rd_data_count
);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file ddr_sync_fifo.vhd when simulating
-- the core, ddr_sync_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo.xco 0 → 100644
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##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Thu Jul 2 17:09:37 2015
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=ddr_sync_fifo
CSET data_count=false
CSET data_count_width=15
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=32765
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=32764
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=18
CSET input_depth=32768
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=36
CSET output_depth=16384
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=true
CSET read_data_count_width=6
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=15
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 2ced3ed7
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo.xise 0 → 100644
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hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/doc/fifo_generator_v9_3_readme.txt 0 → 100644
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CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
Release Date: December 18, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURE HISTORY
3.1 ISE
- ISE 14.4 software support
3.2 Vivado
- 2012.4 software support
- IP level constraint for Built-in FIFO reset synchronizer
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The following are known issues for v9.3 Rev 1 of this core at time of release:
1. Importing an XCO file alters the XCO configurations
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
CR 467240
AR 31379
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
For more information and additional workaround see Answer Record 41099.
5.2 Vivado
The following are known issues for v9.3 Rev 1 of this core at time of release:
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
CR 665836
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/example_design/ddr_sync_fifo_exdes.ucf 0 → 100644
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################################################################################
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "RD_CLK" TNM_NET = "RD_CLK";
NET "WR_CLK" TNM_NET = "WR_CLK";
TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ;
TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ;
################################################################################
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/example_design/ddr_sync_fifo_exdes.vhd 0 → 100644
View file @ bcbef14c
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ddr_sync_fifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ddr_sync_fifo_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(18-1 DOWNTO 0);
DOUT : OUT std_logic_vector(36-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end ddr_sync_fifo_exdes;
architecture xilinx of ddr_sync_fifo_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component ddr_sync_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(18-1 DOWNTO 0);
DOUT : OUT std_logic_vector(36-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : ddr_sync_fifo
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/fifo_generator_v9_3_readme.txt 0 → 100644
View file @ bcbef14c
CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
Release Date: December 18, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURE HISTORY
3.1 ISE
- ISE 14.4 software support
3.2 Vivado
- 2012.4 software support
- IP level constraint for Built-in FIFO reset synchronizer
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The following are known issues for v9.3 Rev 1 of this core at time of release:
1. Importing an XCO file alters the XCO configurations
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
CR 467240
AR 31379
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
For more information and additional workaround see Answer Record 41099.
5.2 Vivado
The following are known issues for v9.3 Rev 1 of this core at time of release:
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
CR 665836
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/implement.bat 0 → 100644
View file @ bcbef14c
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
::
:: This file contains confidential and proprietary information
:: of Xilinx, Inc. and is protected under U.S. and
:: international copyright and other intellectual property
:: laws.
::
:: DISCLAIMER
:: This disclaimer is not a license and does not grant any
:: rights to the materials distributed herewith. Except as
:: otherwise provided in a valid license issued to you by
:: Xilinx, and to the maximum extent permitted by applicable
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
:: (2) Xilinx shall not be liable (whether in contract or tort,
:: including negligence, or under any other theory of
:: liability) for any loss or damage of any kind or nature
:: related to, arising under or in connection with these
:: materials, including for any direct, or any indirect,
:: special, incidental, or consequential loss or damage
:: (including loss of data, profits, goodwill, or any type of
:: loss or damage suffered as a result of any action brought
:: by a third party) even if such damage or loss was
:: reasonably foreseeable or Xilinx had been advised of the
:: possibility of the same.
::
:: CRITICAL APPLICATIONS
:: Xilinx products are not designed or intended to be fail-
:: safe, or for use in any application requiring fail-safe
:: performance, such as life-support or safety devices or
:: systems, Class III medical devices, nuclear facilities,
:: applications related to the deployment of airbags, or any
:: other applications that could lead to death, personal
:: injury, or severe property or environmental damage
:: (individually and collectively, "Critical
:: Applications"). Customer assumes the sole risk and
:: liability of any use of Xilinx products in Critical
:: Applications, subject only to applicable laws and
:: regulations governing limitations on product liability.
::
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
:: PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy ddr_sync_fifo_exdes.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\ddr_sync_fifo.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\ddr_sync_fifo_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx45t-fgg484-2 -sd ../../../ ddr_sync_fifo_exdes
echo 'Running map'
map ddr_sync_fifo_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -tm ddr_sync_fifo_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/implement.sh 0 → 100644
View file @ bcbef14c
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp ddr_sync_fifo_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../ddr_sync_fifo.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/ddr_sync_fifo_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx45t-fgg484-2 -sd ../../../ ddr_sync_fifo_exdes
echo 'Running map'
map ddr_sync_fifo_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -tm ddr_sync_fifo_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/implement_synplify.bat 0 → 100644
View file @ bcbef14c
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
::
:: This file contains confidential and proprietary information
:: of Xilinx, Inc. and is protected under U.S. and
:: international copyright and other intellectual property
:: laws.
::
:: DISCLAIMER
:: This disclaimer is not a license and does not grant any
:: rights to the materials distributed herewith. Except as
:: otherwise provided in a valid license issued to you by
:: Xilinx, and to the maximum extent permitted by applicable
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
:: (2) Xilinx shall not be liable (whether in contract or tort,
:: including negligence, or under any other theory of
:: liability) for any loss or damage of any kind or nature
:: related to, arising under or in connection with these
:: materials, including for any direct, or any indirect,
:: special, incidental, or consequential loss or damage
:: (including loss of data, profits, goodwill, or any type of
:: loss or damage suffered as a result of any action brought
:: by a third party) even if such damage or loss was
:: reasonably foreseeable or Xilinx had been advised of the
:: possibility of the same.
::
:: CRITICAL APPLICATIONS
:: Xilinx products are not designed or intended to be fail-
:: safe, or for use in any application requiring fail-safe
:: performance, such as life-support or safety devices or
:: systems, Class III medical devices, nuclear facilities,
:: applications related to the deployment of airbags, or any
:: other applications that could lead to death, personal
:: injury, or severe property or environmental damage
:: (individually and collectively, "Critical
:: Applications"). Customer assumes the sole risk and
:: liability of any use of Xilinx products in Critical
:: Applications, subject only to applicable laws and
:: regulations governing limitations on product liability.
::
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
:: PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\ddr_sync_fifo.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\ddr_sync_fifo_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx45t-fgg484-2 -sd ../../../ ddr_sync_fifo_exdes
echo 'Running map'
map ddr_sync_fifo_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -tm ddr_sync_fifo_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/implement_synplify.sh 0 → 100644
View file @ bcbef14c
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../ddr_sync_fifo.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/ddr_sync_fifo_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx45t-fgg484-2 -sd ../../../ ddr_sync_fifo_exdes
echo 'Running map'
map ddr_sync_fifo_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -tm ddr_sync_fifo_exdes -pcf mapped.pcf -w routed.ncd routed.vhd
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/planAhead_ise.bat 0 → 100644
View file @ bcbef14c
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
::
:: This file contains confidential and proprietary information
:: of Xilinx, Inc. and is protected under U.S. and
:: international copyright and other intellectual property
:: laws.
::
:: DISCLAIMER
:: This disclaimer is not a license and does not grant any
:: rights to the materials distributed herewith. Except as
:: otherwise provided in a valid license issued to you by
:: Xilinx, and to the maximum extent permitted by applicable
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
:: (2) Xilinx shall not be liable (whether in contract or tort,
:: including negligence, or under any other theory of
:: liability) for any loss or damage of any kind or nature
:: related to, arising under or in connection with these
:: materials, including for any direct, or any indirect,
:: special, incidental, or consequential loss or damage
:: (including loss of data, profits, goodwill, or any type of
:: loss or damage suffered as a result of any action brought
:: by a third party) even if such damage or loss was
:: reasonably foreseeable or Xilinx had been advised of the
:: possibility of the same.
::
:: CRITICAL APPLICATIONS
:: Xilinx products are not designed or intended to be fail-
:: safe, or for use in any application requiring fail-safe
:: performance, such as life-support or safety devices or
:: systems, Class III medical devices, nuclear facilities,
:: applications related to the deployment of airbags, or any
:: other applications that could lead to death, personal
:: injury, or severe property or environmental damage
:: (individually and collectively, "Critical
:: Applications"). Customer assumes the sole risk and
:: liability of any use of Xilinx products in Critical
:: Applications, subject only to applicable laws and
:: regulations governing limitations on product liability.
::
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
:: PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\ddr_sync_fifo.ngc .
planAhead -mode batch -source ..\planAhead_ise.tcl
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/planAhead_ise.sh 0 → 100644
View file @ bcbef14c
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../ddr_sync_fifo.ngc .
planAhead -mode batch -source ../planAhead_ise.tcl
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/planAhead_ise.tcl 0 → 100644
View file @ bcbef14c
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc6slx45tfgg484-2
set projName ddr_sync_fifo
set design ddr_sync_fifo
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module ddr_sync_fifo_exdes
add_files -norecurse {../../example_design/ddr_sync_fifo_exdes.vhd}
add_files -norecurse {./ddr_sync_fifo.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/ddr_sync_fifo_exdes.xdc}
set_property top ddr_sync_fifo_exdes [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module ddr_sync_fifo_exdes -file routed.sdf
write_vhdl -mode sim routed.vhd
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/xst.prj 0 → 100644
View file @ bcbef14c
work ../example_design/ddr_sync_fifo_exdes.vhd
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/implement/xst.scr 0 → 100644
View file @ bcbef14c
run
-ifmt VHDL
-ent ddr_sync_fifo_exdes
-p xc6slx45t-fgg484-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn ddr_sync_fifo_exdes
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/simulation/ddr_sync_fifo_dgen.vhd 0 → 100644
View file @ bcbef14c
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ddr_sync_fifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.ddr_sync_fifo_pkg.ALL;
ENTITY ddr_sync_fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF ddr_sync_fifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:ddr_sync_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/simulation/ddr_sync_fifo_dverif.vhd 0 → 100644
View file @ bcbef14c
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ddr_sync_fifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.ddr_sync_fifo_pkg.ALL;
ENTITY ddr_sync_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF ddr_sync_fifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:ddr_sync_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/simulation/ddr_sync_fifo_rng.vhd 0 → 100644
View file @ bcbef14c
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ddr_sync_fifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY ddr_sync_fifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF ddr_sync_fifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
hdl/ip_cores/ddr_sync_fifo/ddr_sync_fifo/simulation/ddr_sync_fifo_tb.vhd 0 → 100644
View file @ bcbef14c
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ddr_sync_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.ddr_sync_fifo_pkg.ALL;
ENTITY ddr_sync_fifo_tb IS
END ENTITY;
ARCHITECTURE ddr_sync_fifo_arch OF ddr_sync_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from ddr_sync_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of ddr_sync_fifo_synth
ddr_sync_fifo_synth_inst:ddr_sync_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 38
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
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dump -file ddr_sync_fifo.vpd -type VPD
dump -add ddr_sync_fifo_tb
run
quit
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