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Last edited by Vasco Guita

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SIS1160 PCI-L I/O add on

The sis1160-pci-io is a front-end PCI board with LEMO connectors to interface with the GPIO interconnect pins (J70) of the SIS1160 FMC carrier, which is a commercial PCIe FMC carrier provided by Struck Innovative Systeme (SIS). This auxiliary board gets inserted in a computer, next to the SIS1160 carrier, with a PCI bracket (but does not use the PCI bus), and has 6 digital channels. Four of them are LVDS and two are LVTLL. The direction of every signal or pair can be configured to act as input or output from/into the SIS1160 carrier.

The SIS1160 carrier board is used together with the SFMC01 digitizer, that contains the AD9689 analog-to-digital converter. The current repository features thus an auxiliary board that allows the integration of "events" or "GPIO markers" into the ADC datastream. The lower bit of the acquired ADC data word of each ADC channel can be configured (via the SIS1160 API) to store the status of two selected input channels of the PCI-L I/O add on. Furthermore, the other (output) channels can be used for monitoring the trigger or clock and synchronizing with additional external hardware.

PCI-L I/O add-on SIS1160 FMC carrier with interconnect
I/O add-on SIS1160

Functional specifications

  • Backend:

    • Board is supplied by PCI 6-pin PEG ATX power (J10) on the back end.
    • J11 (Molex 878331031) on the back end connects via flat cable (Amphenol 191-2815-010) to J70 of SIS1160.

  • Frontend: 6 digital channels (LEMO connectors)

    • 4 LVDS input/output ports (LEMO 00 triaxial connectors), non-isolated.
    • 2 LVTTL input/output ports (LEMO 00 coaxial connectors), non-isolated
    • Note that if the holes in the PCI bracket for the LEMO are too tight, you will need to isolate with wrap the LEMO connector sides to avoid breaking the galvanic isolation.

  • Predefined pin function on J1-J6 (add-on board) interfacing J70 (SIS1160 board):

    • The direction of every pair/signal at J70 can be controlled individually.
    • J1 <=> J70-[1,2]: [CLK_P, CLK_N] LVDS Synchronous clock source distribution
    • J2 <=> J70-[3,4]: [TRIG_P, TRIG_N] LVDS (Suggestion) Global trigger distribution, firmware defined
    • J3 <=> J70-[5,6]: [TIMES_P, TIMES_N] LVDS (Suggestion) Global timestamp distribution, firmware defined
    • J4 <=> J70-[7,8]: [USER1_P, USER1_N] LVDS General purpose
    • J5 <=> J70-[9]: [USER2_L] LVTTL General purpose, single ended, open drain
    • J6 <=> J70-[10]: [USER3_L] LVTTL General purpose, single ended, open drain

  • Programmable termination on SIS1160 via switch SW70:

    • SW70-1: When ON, enable 100Ω Termination for CLK_P/CLK_N
    • SW70-2: When ON, enable 100Ω Termination for TRIG_P/TRIG_N
    • SW70-3: When ON, enable 100Ω Termination for TIMES_P/TIMES_N
    • SW70-4: When ON, enable 100Ω Termination for USER1_P/USER1_N
    • SW70-5: When ON, enable 4.7kΩ Pullup to 3.3V on USER2_L
    • SW70-6: When ON, enable 4.7kΩ Pullup to 3.3V on USER3_L

  • 4-layer PCB (Layer buildup is ML4-1mm)

    • GND-LVDS isolation height: 0.232 mm
    • Trace edge-coupled surface microstrip width: 0.25 mm, gap: 0.20 mm, height: 0.035mm
    • All four LVDS signal pairs are skew and length-matched (100 mm), but not the LVTTL ones.

  • Source files are in KiCAD v6.0.3

Project information

Contacts

Commercial producers

  • Not commercially available

Project

  • Fernando Hueso González - IFIC - Instituto de Física Corpuscular (CSIC/UV), Spain
  • Antonio Fernández Prieto - IGFAE - Instituto Galego de Física de Altas Enerxías (USC HEP), Spain
  • Thanks to Struck SIS for guidance (M. Kirsch, T. Hauepke, T. Fritzke, O. Topalova)
  • Thanks to JV Casaña and the IFIC electronics service for manufacturing and debugging.
  • It is developed in the context of the coaxial prompt gamma-ray project and is funded by Generalitat Valenciana under grant number CDEIGENT/2019/11.

Project Status

Date Event
01-10-2020 Start of project.
13-11-2020 One prototype card built. Has some bugs.
02-06-2021 CERN OHL-W v2+ license added.
10-06-2021 Work in progress: galvanic isolation of LVTLL signals.
17-03-2022 Upgrade KiCad files to v6.
16-09-2022 New PCB revision with galvanic isolation sent to production.