... | ... | @@ -94,18 +94,10 @@ Virtex-6 FPGAs |
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Check Xilinx website for latest version:
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http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_meminterfacecontrol_mig.htm
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Date </b></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>23-11-2011</td>
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<td>First prototype in simulation (QDRII memory controller docs and code)</td>
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</tr>
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</tbody>
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</table>
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|**Date**|**Event**|
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|----|----|
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|23-11-2011|First prototype in simulation (QDRII memory controller docs and code)|
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... | ... | @@ -113,4 +105,4 @@ http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_meminterfa |
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* [CY7C1314CV18.pdf](/uploads/9c4ac2e7b1c984bd913fafa1e1347f37/CY7C1314CV18.pdf)
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* [ug406.pdf](/uploads/ce0faa4e38d3d605d140c8ec4cde59c7/ug406.pdf)
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* [xapp886.pdf](/uploads/3af02b0ca5af64a8afe70c7dcfda50c6/xapp886.pdf)
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* [QDRII_controller_diagramv0.jpg](/uploads/73be4991980a3e38886b6d73620e9271/QDRII_controller_diagramv0.jpg) |
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\ No newline at end of file |
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* [QDRII_controller_diagramv0.jpg](/uploads/73be4991980a3e38886b6d73620e9271/QDRII_controller_diagramv0.jpg) |