... | ... | @@ -18,16 +18,17 @@ This project is a PXIe system controller that is based on a [COM Express](https: |
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- Compliance with [COM Express](https://www.picmg.org/openstandards/com-express/) basic Pin-out type 6
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- Compliance with [PXIe standard for 3U system controller slot](http://www.pxisa.org/userfiles/files/Specifications/PXIEXPRESS_HW_SPEC_R1.PDF)
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- PCIe lane should be designed to meet PCIe GEN 3
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- 16x PCIe lanes should be routed to a 4 link PXIe backplane connector
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- Possibility to install a full size mSATA SSD
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- 1x RS232 port DSUB9 connector on front panel
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- 4x USB 2.0 on the front panel
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- 2x USB 3.0 on the front panel
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- 1x 10/100/1000 Ethernet LAN on the front panel
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- 1x DisplayPort on the front panel
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- PCIe lane designed to meet PCIe GEN 3 specification
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- 16x PCIe lanes routed to the PXIe backplane connector
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- PXIe trigger controller (FPGA)
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- 1x SMB PXIe trigger line on front panel
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- Possibility to install a full size mSATA SSD (supports mini mSATA)
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- Front panel
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- 1x RS232 port DSUB9 connector
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- 4x USB 2.0
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- 2x USB 3.0
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- 1x 10/100/1000 Ethernet LAN
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- 1x DisplayPort
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- 1x SMB PXIe trigger line
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... | ... | @@ -67,7 +68,8 @@ This project is a PXIe system controller that is based on a [COM Express](https: |
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| 27-06-2019| Review of pre-study. |
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| 24-10-2019| Start of schematics design |
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| 05-12-2019| [First version of schematics design (v0.1)](PXIeCOMe-V0_1) made. Review will be held. |
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| 09-04-2020| Schematics review held. |
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23 March 2020 |
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\ No newline at end of file |
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9 April 2020 |
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