... | ... | @@ -10,17 +10,17 @@ This project is a PXIe system controller that is based on a [COM Express](https: |
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## Main Features
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- Compliance with [COM Express](https://www.picmg.org/openstandards/com-express/) Compact Pin-out type 6
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- Compliance with [PXIe standard for system controller slot](http://www.pxisa.org/userfiles/files/Specifications/PXIEXPRESS_HW_SPEC_R1.PDF)
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- Compliance with [COM Express](https://www.picmg.org/openstandards/com-express/) basic Pin-out type 6
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- Compliance with [PXIe standard for 3U system controller slot](http://www.pxisa.org/userfiles/files/Specifications/PXIEXPRESS_HW_SPEC_R1.PDF)
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- PCIe lane should be designed to meet PCIe GEN 3
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- 16x PCIe lanes should be routed to PXIe backplane connector
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- Possibility to install a mSATA SSD
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- 1x RS232/422/485 port DSUB9 connector on front panel
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- 16x PCIe lanes should be routed to a 4 link PXIe backplane connector
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- Possibility to install a full size mSATA SSD
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- 1x RS232 port DSUB9 connector on front panel
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- 4x USB 2.0 on the front panel
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- 2x USB 3.0 on the front panel
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- 2x 10/100/1000 Ethernet LAN on the front panel
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- 1x 10/100/1000 Ethernet LAN on the front panel
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- 1x DisplayPort on the front panel
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- PXIe trigger controller connected to COM Express LPC bus
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- PXIe trigger controller with an FPGA
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- 1x SMB PXIe trigger line on front panel
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