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Production Test Suite
Commit a5fafd0e authored by Matthieu Cattin's avatar Matthieu Cattin
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Add RSTOUT33 assert/de-assert cycle to gennum class.

parent 91306153
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test/fmcadc100m14b4cha/python/gn4124.py
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......@@ -19,6 +19,7 @@ class CGN4124:
# GN4124 chip registers (BAR4)
GN4124_BAR = 0x4
R_PCI_SYS_CFG = 0x800
R_CLK_CSR = 0x808
R_INT_CFG0 = 0x820
R_GPIO_DIR_MODE = 0xA04
......@@ -96,6 +97,13 @@ class CGN4124:
# Add here reading of the interrupt source (once the irq core will be present)
return self.bus.irqwait()
# GN4124 RSTOUT33 assert/de-assert cycle
def rstout33_cycle(self):
# assert RSTOUT33 pin
self.wr_reg(self.GN4124_BAR, self.R_PCI_SYS_CFG, 0x00021040)
# de-assert RSTOUT33 pin
self.wr_reg(self.GN4124_BAR, self.R_PCI_SYS_CFG, 0x00025000)
# GN4124 interrupt configuration
def set_interrupt_config(self):
# Set interrupt line from FPGA (GPIO8) as input
......
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