Merge branch 'fix-tests'

8b02c3af · Samuel Iglesias Gonsalvez · 3e9c9a39 · eb35fe66 · 8b02c3af · 8b02c3af
Commit 8b02c3af authored Jul 15, 2011 by Samuel Iglesias Gonsalvez
21 changed files
--- a/gnurabbit-2010-08-05/kernel/rawrabbit.c
+++ b/gnurabbit-2010-08-05/kernel/rawrabbit.c
@@ -57,19 +57,25 @@ irqreturn_t rr_interrupt(int irq, void *devid)
 * One device id only is supported. 
 */

-static struct pci_device_id rr_idtable[2]; /* last must be zero */
+static struct pci_device_id rr_idtable[3]; /* last must be zero */

 static void rr_fill_table(struct rr_dev *dev)
 {
 	if (dev->devsel->subvendor == RR_DEVSEL_UNUSED) {
-		dev->id_table->subvendor = PCI_ANY_ID;
-		dev->id_table->subdevice = PCI_ANY_ID;
+		dev->id_table[0].subvendor = PCI_ANY_ID;
+		dev->id_table[0].subdevice = PCI_ANY_ID;
 	} else {
-		dev->id_table->subvendor = dev->devsel->subvendor;
-		dev->id_table->subdevice = dev->devsel->subdevice;
+		dev->id_table[0].subvendor = dev->devsel->subvendor;
+		dev->id_table[0].subdevice = dev->devsel->subdevice;
 	}
-	dev->id_table->vendor = dev->devsel->vendor;
-	dev->id_table->device = dev->devsel->device;
+	dev->id_table[0].vendor = dev->devsel->vendor;
+	dev->id_table[0].device = dev->devsel->device;
+
+	
+	dev->id_table[1].vendor = RR_CERN_VENDOR;
+	dev->id_table[1].device = RR_CERN_DEVICE;
+	dev->id_table[1].subvendor = PCI_ANY_ID;
+	dev->id_table[1].subdevice = PCI_ANY_ID;
 }

 static int rr_fill_table_and_probe(struct rr_dev *dev)

--- a/gnurabbit-2010-08-05/kernel/rawrabbit.h
+++ b/gnurabbit-2010-08-05/kernel/rawrabbit.h
@@ -49,6 +49,8 @@ struct rr_dev {
 /* By default, the driver registers for this vendor/devid */
 #define RR_DEFAULT_VENDOR	0x1a39
 #define RR_DEFAULT_DEVICE	0x0004
+#define RR_CERN_VENDOR		0x10dc
+#define RR_CERN_DEVICE		0x018d

 #define RR_DEFAULT_BUFSIZE	(1<<20)		/* 1MB */
 #define RR_PLIST_SIZE		4096		/* no PAGE_SIZE in user space */

--- a/test/example/python/test00.py
+++ b/test/example/python/test00.py
+#!   /usr/bin/env   python
+#    coding: utf8
+
+# Copyright <company>, 2011
+# Author: John Doe <john.doe@example.com>
+# Licence: GPL v2 or later.
+# Website: http://www.ohwr.org
+
+import sys
+import rr		# Needed for accessing the rawrabbit driver
+import time
+import os
+from tpsexcept import * # Declaration of Exceptions
+
+"""
+test00: example test which prints 'hello <name>'
+"""
+
+# Helping class to access to the chips or to do common things
+# It is recommended to have them at the same file to not need
+# extra dependencies, however it is not mandatory.
+class CTest:
+	
+	def __init__(self, bus, base):
+		self.bus = bus;
+		self.base =base;
+	
+	def hello(self, val):
+		print "Hello " + val
+	
+
+def main (default_directory='.'):
+
+	# The following commented code just loads the firmware 
+	# using a program fpga_loader. The user can use its own.
+
+	"""
+	path_fpga_loader = '../firmwares/fpga_loader';
+	path_firmware = '../firmwares/test00.bin';
+    	
+	firmware_loader = os.path.join(default_directory, path_fpga_loader)
+    	bitstream = os.path.join(default_directory, path_firmware)
+    	os.system( firmware_loader + ' ' + bitstream)
+    	time.sleep(2);
+	"""
+
+	# After loading the firmware, we are ready to access to the registers.
+	gennum = rr.Gennum();
+
+	# Instantiate CTest.
+	# The parameters are the Gennum variable and the Wishbone base address
+	# of the corresponding WB slave. At this case, we don't have a WB slave.
+	hi = CTest(gennum, 0x40000); 
+	
+	# This function just print in command line 'Hello <name>' but it can be
+	# much more complex than that: accessing to the board, changing register's
+	# values, etc.
+	hi.hello("world")
+
+
+# This code calls the 'main' function when the program is executed by command-line
+# using './test00.py' or 'python test00.py'. In case of importing this Python program
+# into another one, you should call it as 'test00.main(path_of_tests)' 
+if __name__ == '__main__' :
+	main();
+
--- a/test/spec/README
+++ b/test/spec/README
@@ -16,11 +16,13 @@ This batch of test makes a connectivity test of the SPEC's components.
 	- test01: checks the low speed pins of FMC connector (low count connector).
 	- test02: checks the EEPROM of the GENNUM chip. 
 	- test03: loads a firmware file to Flash memory and boots from it. The FW just blinks the front-panel leds using the buttons.
-	- test04: not present yet. It should be SFP connectivity test.
+	- test04: checks the EEPROM present in the SFP connector. Reads the type.
 	- test05: checks SATA ports and high speed pins on FMC connector (low count connector).
 	- test06: checks Silabs SI570 oscillator.
 	- test07: checks data and address lines of DDR memory.
 	- test08: checks PLL and rest of oscillators on SPEC board.
+	- test09: reads Temperature sensor's unique ID.
+	- test10: overwrites the GENNUM's EEPROM to setup VENDOR ID and DEVICE ID to the correct values.

 This tests are made to work stand-alone too. So, it is possible to call each one using 'python test0x.py'


--- a/test/spec/firmwares/test04.bin
+++ b/test/spec/firmwares/test04.bin
--- a/test/spec/firmwares/test09.bin
+++ b/test/spec/firmwares/test09.bin
--- a/test/spec/hdl/test00/README
+++ b/test/spec/hdl/test00/README
-------------------------------------------------------------------------------
--------------------------------    TEST 1    ---------------------------------
-------------------------------------------------------------------------------
-
-1.- WHAT IS INCLUDED
-
-  A.- A top VHDL in which 3 wishbone slaves can be addressed. Only the first
-      two are used. This two wishbone slaves correspond to the I2C master that
-      connect to i2c devices in fmc-carrier-tester: I2C_A, I2C_B.
-      Its wishbone mappings are
-        - I2C_A: 0x40000
-        - I2C_B: 0x80000
-  B.- "test00.bin" which is the bitstream for programming spec FPGA with the
-      aforementioned configuration.
-  C.- "test00.py" that it's a python test which is an aggregate of the rest
-      of python code.
-
-This test checks the voltage values of the power supply pins on the FMC.
--- a/test/spec/hdl/test00/spec_ddr_test_top.vhd
+++ b/test/spec/hdl/test00/spec_ddr_test_top.vhd
--- a/test/spec/hdl/test00/spec_top.ucf
+++ b/test/spec/hdl/test00/spec_top.ucf
--- a/test/spec/python/eeprom_original.dat
+++ b/test/spec/python/eeprom_original.dat
+F808 0809F03C
+F808 0001F03C
+F05C 00008002
+F060 00005840
+F850 00000008
+F800 00025000
+FFFF 00000000
--- a/test/spec/python/eeprom_vid.dat
+++ b/test/spec/python/eeprom_vid.dat
+F808 0809F03C
+F808 0001F03C
+F000 018D10DC
+F008 00000003
+F05C 00008002
+F060 00005840
+F850 00000008
+F800 00025000
+FFFF 00000000
+
\ No newline at end of file
--- a/test/spec/python/libfpga_loader.so
+++ b/test/spec/python/libfpga_loader.so
--- a/test/spec/python/test00.py
+++ b/test/spec/python/test00.py
@@ -70,7 +70,7 @@ class COpenCoresI2C:
 		self.wait_busy()
 		
 		if(self.rd_reg(self.R_SR) & self.SR_RXACK):
-			raise Exception('No ACK upon address (device 0x%x not connected?)' % addr)
+			raise TpsError('Failed I2C communication. No ACK upon address (device 0x%x not connected?)' % addr)

 	def write(self, data, last):
 		self.wr_reg(self.R_TXR, data);
@@ -80,7 +80,7 @@ class COpenCoresI2C:
 		self.wr_reg(self.R_CR, cmd);
 		self.wait_busy();
 		if(self.rd_reg(self.R_SR) & self.SR_RXACK):
-			raise Exception('No ACK upon write')
+			raise TpsError('Failed I2C communication. No ACK upon write')

 	def read(self, last):
 		cmd = self.CR_RD;
@@ -137,6 +137,11 @@ class ADC_AD7997:

 def adc_value(value) :
 	return str(2.495 * (0x3FF & (value >> 2)) / 1024); # 10 bits
+
+def adc_convert_to_real_value (nr_value, value) :
+	ratio = {'8': 0.6666, '7': 0.1666, '6': 0.52381};
+	return str(float(value) / ratio[str(nr_value)]) 
+	
 	
 def main (default_directory='.'):

@@ -166,39 +171,17 @@ def main (default_directory='.'):
 	value1 = adc_value(adc.rd_reg16(0x80));

 	# Check the values of the ADC.
-	if(float(value8) < 1.61) or (float(value8) > 1.73) :
-		raise TpsError ("Error in VS_VADJ, value x=" + value8 + ". x > 1.73 V or x < 1.61 V")
-	print "VS_VADJ = " + value8
-
-	if(float(value7) < 1.90) or (float(value7) > 2.11):
-		raise TpsError ("Error in VS_P12V_x, value x=" + value7 + ". x< 1.90 V or x > 2.11 V")
-	print "VS_P12V_x = " + value7
+	if(float(value8) < 1.58) or (float(value8) > 1.75) :
+		raise TpsError ("Error in VS_VADJ (2.5V) measured "+ adc_convert_to_real_value(8, value8) + "V.") 
+	print "VS_VADJ = " + adc_convert_to_real_value(8, value8)

-	if(float(value6) < 1.66) or (float(value6) > 1.80):
-		raise TpsError ("Error in VS_P3V3_x, value x=" + value6 + ". x < 1.66 V or x > 1.80 V")
-	print "VS_P3V3_x = " + value6
-
-"""
-	if(float(value5) < 2.52) :
-		print "Error in P5V_BI, value " + value5 + " < 2.52 V"
-	print "P5V_BI = " + value5
+	if(float(value7) < 1.88) or (float(value7) > 2.13):
+		raise TpsError ("Error in VS_P12V_x (12V) measured "+ adc_convert_to_real_value(7, value7) + "V.") 
+	print "VS_P12V_x = " + adc_convert_to_real_value(7, value7)

-	if(float(value4) > 2.0) :
-		print "Error in M2V_BI, value " + value4 + " > 2.0 V"
-	print "M2V_BI = " + value4
-
-	if(float(value3) > 2.28) :
-		print "Error in M5V2_BI, value " + value3 + " > 2.28 V"
-	print "M5V2_BI = " + value3
-
-	if(float(value2) > 2.4) :
-		print "Error in M12V_BI, value " + value2 + " > 2.4 V"
-	print "M12V_BI = " + value2
-
-	if(float(value1) < 2.0) :
-		print "Error in P12V_BI, value " + value1 + " < 2.0 V"
-	print "P12V_BI = " + value1
-"""
+	if(float(value6) < 1.64) or (float(value6) > 1.82):
+		raise TpsError ("Error in VS_P3V3_x (3.3V) measured "+ adc_convert_to_real_value(6, value6) + "V.") 
+	print "VS_P3V3_x = " + adc_convert_to_real_value(6, value6)

 if __name__ == '__main__' :
 	main();

--- a/test/spec/python/test04.py
+++ b/test/spec/python/test04.py
+#!   /usr/bin/env   python
+#    coding: utf8
+
+# Copyright CERN, 2011
+# Author: Samuel Iglesias Gonsalvez <siglesia@cern.ch>
+# Licence: GPL v2 or later.
+# Website: http://www.ohwr.org
+
+import sys
+import rr
+import time
+import os
+from tpsexcept import *
+
+"""
+test00: checks the presence of the SFP connector and reads the type of connector
+"""
+
+BASE_GPIO = 0x40000
+BASE_MINIC = 0xc0000
+GPIO_CODR = 0x0
+GPIO_SODR = 0x4
+GPIO_PSR = 0xc
+        	
+class COpenCoresI2C:
+	R_PREL = 0x0
+	R_PREH = 0x4
+	R_CTR = 0x8
+	R_TXR = 0xC
+	R_RXR = 0xC
+	R_CR = 0x10
+	R_SR = 0x10
+	
+	CTR_EN = (1<<7)
+	
+	CR_STA = (1<<7)
+	CR_STO = (1<<6)
+	CR_WR = (1<<4)
+	CR_RD = (1<<5)
+	CR_NACK = (1<<3)
+	
+	SR_RXACK = (1<<7)
+	SR_TIP = (1<<1)
+	
+	
+	def wr_reg(self, addr, val):
+		self.bus.iwrite(0, self.base +  addr, 4, val)
+
+	def rd_reg(self,addr):
+		return self.bus.iread(0, self.base + addr, 4)
+	
+	def __init__(self, bus, base, prescaler):
+		self.bus = bus;
+		self.base =base;
+		self.wr_reg(self.R_CTR, 0);
+		self.wr_reg(self.R_PREL, (prescaler & 0xff))
+		self.wr_reg(self.R_PREH, (prescaler >> 8))
+		self.wr_reg(self.R_CTR, self.CTR_EN);
+	
+	def wait_busy(self):
+		while(self.rd_reg(self.R_SR) & self.SR_TIP):
+			pass
+	
+	def start(self, addr, write_mode):
+		addr = addr << 1
+		if(write_mode == False):
+			addr = addr | 1;
+		self.wr_reg(self.R_TXR, addr);
+		self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR);
+		self.wait_busy()
+		
+		if(self.rd_reg(self.R_SR) & self.SR_RXACK):
+			raise Exception('No ACK upon address (device 0x%x not connected?)' % addr)
+
+	def write(self, data, last):
+		self.wr_reg(self.R_TXR, data);
+		cmd = self.CR_WR;
+		if(last):
+			cmd = cmd | self.CR_STO;
+		self.wr_reg(self.R_CR, cmd);
+		self.wait_busy();
+		if(self.rd_reg(self.R_SR) & self.SR_RXACK):
+			raise Exception('No ACK upon write')
+
+	def read(self, last):
+		cmd = self.CR_RD;
+		if(last):
+			cmd = cmd | self.CR_STO | self.CR_NACK;
+		self.wr_reg(self.R_CR, cmd);
+		self.wait_busy();
+		
+		return self.rd_reg(self.R_RXR);
+
+class EEPROM_SFP:
+	def __init__(self, i2c, addr):
+		self.i2c = i2c;
+		self.addr = addr;
+
+	def wr_reg16(self, addr, value):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		tmp = (value >> 8) & 0xFF;
+		self.i2c.write(value, False);
+		tmp = value & 0xFF;
+		self.i2c.write(value, True)
+
+	def wr_reg8(self, addr, value):
+		self.i2c.start(self.addr, True); # write cycle
+		self.i2c.write(addr, False);
+		self.i2c.write(value, True);	
+
+	def rd_reg16(self, addr):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		self.i2c.start(self.addr, False);
+		tmp_MSB = self.i2c.read(False);
+		tmp_LSB = self.i2c.read(True);
+		value = (tmp_MSB << 8) | tmp_LSB;
+		return value;
+
+	def rd_reg8(self, addr):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		self.i2c.start(self.addr, False);
+		return self.i2c.read(True);	
+
+
+def main (default_directory='.'):
+
+	path_fpga_loader = '../firmwares/fpga_loader';
+	path_firmware = '../firmwares/test04.bin';
+    	
+	firmware_loader = os.path.join(default_directory, path_fpga_loader)
+    	bitstream = os.path.join(default_directory, path_firmware)
+    	os.system( firmware_loader + ' ' + bitstream)
+
+    	time.sleep(2);
+    
+	gennum = rr.Gennum();
+
+	i2c = COpenCoresI2C(gennum, 0x40000, 99); # Prescaler value calculated using 50 MHz clock
+	eeprom = EEPROM_SFP(i2c, 0x50);
+	type = eeprom.rd_reg8(0x0); 
+
+	print "Type of serial transceiver: " + hex(type)
+	if (type == 3) :
+		print "Type is correct"
+	else :
+		raise TpsError("Wrong type of connector. It should be 0x3")
+
+if __name__ == '__main__' :
+	main();
+
--- a/test/spec/python/test05.py
+++ b/test/spec/python/test05.py
@@ -134,6 +134,148 @@ class SWITCH_ADN4600:
 	def enable_tx(self, channel) :
 		self.wr_reg8(0xC0 + 0x8*channel, (1 << 5))

+class CSI570 :
+	
+	HS_N1_DIV = 0x7;
+	REF_FREQ_37_32 = 0x8;
+	REF_FREQ_31_24 = 0x9;
+	REF_FREQ_23_16 = 0xA;
+	REF_FREQ_15_8 = 0xB;
+	REF_FREQ_7_0 = 0xC;
+	RST_MEM_CTRL = 0x87;
+	FREEZE_DCO = 0x89;
+	
+
+	def __init__(self, i2c, addr):
+		self.i2c = i2c;
+		self.addr = addr;
+
+	def wr_reg16(self, addr, value):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		tmp = (value >> 8) & 0xFF;
+		self.i2c.write(value, False);
+		tmp = value & 0xFF;
+		self.i2c.write(value, True)
+
+	def wr_reg8(self, addr, value):
+		self.i2c.start(self.addr, True); # write cycle
+		self.i2c.write(addr, False);
+		self.i2c.write(value, True);	
+
+	def rd_reg16(self, addr):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		self.i2c.start(self.addr, False);
+		tmp_MSB = self.i2c.read(False);
+		tmp_LSB = self.i2c.read(True);
+		value = (tmp_MSB << 8) | tmp_LSB;
+		return value;
+
+	def rd_reg8(self, addr):
+		self.i2c.start(self.addr, True);
+		self.i2c.write(addr, False);
+		self.i2c.start(self.addr, False);
+		return self.i2c.read(True);	
+
+	def calculate_hs(self, hs_div) :
+		convert = {'4': 0, '5': 1, '6': 2, '7':3, '9': 5, '11':7};
+
+		return convert[str(hs_div)];  
+
+
+        def read_setup_oscillator(self) :
+		""" Data saved in internal variables of the class """
+                tmp = self.rd_reg8(self.HS_N1_DIV);
+		self.hs_div = tmp >> 5;
+
+		self.n1 = (tmp & 0x1F) << 2;
+		tmp = self.rd_reg8(self.REF_FREQ_37_32);
+		self.n1 |= tmp >> 6;
+
+		self.rfreq  = (tmp & 0x3F) << 32;
+
+		self.rfreq |= self.rd_reg8(self.REF_FREQ_31_24) << 24;
+		self.rfreq |= self.rd_reg8(self.REF_FREQ_23_16) << 16;
+		self.rfreq |= self.rd_reg8(self.REF_FREQ_15_8)  << 8;
+		self.rfreq |= self.rd_reg8(self.REF_FREQ_7_0);
+
+	
+	def setup_oscillator(self, hs_div, n1_div, rfreq) :
+		""" Setup the oscillator with the given parameters """
+
+		# Freeze the oscillator to setup it
+                self.wr_reg8(self.FREEZE_DCO, (1 << 4));
+
+		# Write setup
+		val = ((hs_div & 0x7) << 5) | (n1_div >> 2)
+		self.wr_reg8(self.HS_N1_DIV, val);
+
+		val = ((n1_div & 0x3) << 6) | (rfreq >> 32);
+		self.wr_reg8(self.REF_FREQ_37_32, val);
+
+		val = (rfreq >> 24) & 0xFF;
+		self.wr_reg8(self.REF_FREQ_31_24, val);
+
+		val = (rfreq >> 16) & 0xFF;
+		self.wr_reg8(self.REF_FREQ_23_16, val);
+
+		val = (rfreq >> 8) & 0xFF;
+		self.wr_reg8(self.REF_FREQ_15_8, val);
+		
+		val = rfreq & 0xFF;
+		self.wr_reg8(self.REF_FREQ_7_0, val);
+
+		self.read_setup_oscillator();
+		print "wrote before confirmation"
+	        print "HS DIV: " + str(self.hs_div);
+                print "N1: " + str(self.n1);
+                print "RFREQ: " + str(self.rfreq);
+
+		# Unfreeze it
+		tmp = self.rd_reg8(self.FREEZE_DCO);
+		self.wr_reg8(self.FREEZE_DCO, tmp & 0xEF);
+
+		self.wr_reg8(self.RST_MEM_CTRL, (1 << 6));
+		while(self.rd_reg8(self.RST_MEM_CTRL) & (1 << 6)): 
+			pass;
+
+
+
+        def setup_frequency(self, freq) :
+            """ Calculate the proper parameters and setup them into the oscillator"""
+
+	    finish = 0;
+	    for N1 in range(0,65) :
+	        if N1 == 0 :
+	            n1 = 1;
+                else :
+                    n1 = N1*2;
+
+                for HSDIV in [4, 5, 6, 7, 9, 11] :
+                    x = freq*HSDIV * n1;
+                    if (x < 5670) and (x > 4850) :
+             	         finish = 1;
+                         freq_dco = x;
+	                 break;
+
+	        if finish :
+	            break;
+
+            if (not finish):
+                 raise TpsError('SI570: Not found a proper setup')
+
+            tmp = freq_dco / 114.28;
+            rfreq = int((tmp * (2**28)));
+	    hsdiv = self.calculate_hs(HSDIV);
+	    n1 = n1 - 1;
+            self.setup_oscillator(hsdiv, n1, rfreq);
+
+	def reset(self) :
+		val = (1 << 7);
+		self.wr_reg8(self.RST_MEM_CTRL, val);
+
+

 class CMinic:
 	OFFSET_EP = 0x4000
@@ -331,6 +473,8 @@ def main (default_directory='.'):
    adn4600.enable_tx(6) # channel 5
    adn4600.enable_tx(7) # channel 4

+    print "------------------------------------"
+    print "Setup ADN4600 chip (crossing point) \n"
    print "adn4600 tx 1-0: " + hex(adn4600.rd_reg8(0xC8)) + " " + hex(adn4600.rd_reg8(0xC0))
    print "adn4600 tx 3-2: " + hex(adn4600.rd_reg8(0xD8)) + " " + hex(adn4600.rd_reg8(0xD0))
    print "adn4600 tx 5-4: " + hex(adn4600.rd_reg8(0xF0)) + " " + hex(adn4600.rd_reg8(0xF8))
@@ -361,6 +505,26 @@ def main (default_directory='.'):

    time.sleep(1)

+    # The address of the SI570 is fixed in the part number
+    si570 = CSI570(i2c, 0x55);
+    si570.read_setup_oscillator()
+
+    print "------------------------------------"
+    print "Original setup of FMC Carrier tester's Si570"
+    print "HS DIV: " + str(si570.hs_div);
+    print "N1: " + str(si570.n1);
+    print "RFREQ: " + str(si570.rfreq);
+    print "\n"
+    time.sleep(1)
+
+    si570.setup_frequency(125)
+    si570.read_setup_oscillator()
+    print "After setup of FMC Carrier tester's Si570 for f_out = 125 MHz:"
+    print "HS DIV: " + str(si570.hs_div);
+    print "N1: " + str(si570.n1);
+    print "RFREQ: " + str(si570.rfreq);
+    print "------------------------------------"
+
    minic_sata = CMinic(gennum, 0x20000, 0);
    minic_sata.init_ep()

@@ -376,7 +540,7 @@ def main (default_directory='.'):
    size = 129;


-    p = Process(target=rx_thread, args=(minic_dp0, size));
+    p = Process(target=rx_thread, args=(minic_sfp, size));
    p.start();
    # Send the data
    time.sleep(1);
@@ -391,7 +555,7 @@ def main (default_directory='.'):

    if (p.is_alive()) :
 	p.terminate();
-	raise TpsError("Test SATA -> DP0: Error in DP0, RX")
+	raise TpsError("Test SATA -> SFP: Error in SFP, RX")
 
    time.sleep(2);

@@ -400,9 +564,9 @@ def main (default_directory='.'):
    # Send the data
    time.sleep(1);

-    print "DP0 tx: "
+    print "SFP tx: "
    for i in range(1,10):
-	minic_dp0.test_tx()
+	minic_sfp.test_tx()
 	time.sleep(1);
 	print "Transmitted [" + str(i) + "]"

@@ -410,19 +574,10 @@ def main (default_directory='.'):

    if (p.is_alive()) :
 	p.terminate();
-	raise TpsError ("Test DP0 -> SATA 0: Error in SATA 0, RX")
+	raise TpsError ("Test SFP -> SATA 0: Error in SATA 0, RX")
 
    time.sleep(2)    

-    ask = "";
-    print "\n*************************************************************"
-    while ((ask != "Y") and (ask != "N")) :
-        ask = raw_input("Please, now connect a SATA cable between FMC tester and SATA 1 connector. Is it done? [Y/N]")
-        ask = ask.upper()
-
-    if (ask == "N") :
-	raise TpsWarning("Test DP0-SATA 1 cancelled");
-

    p = Process(target=rx_thread, args=(minic_dp0, size));
    p.start();

--- a/test/spec/python/test06.py
+++ b/test/spec/python/test06.py
@@ -70,7 +70,7 @@ class COpenCoresI2C:
 		self.wait_busy()
 		
 		if(self.rd_reg(self.R_SR) & self.SR_RXACK):
-			raise TpsError('No ACK upon address (device 0x%x not connected?)' % addr)
+			raise TpsError('Failed I2C. No ACK upon address (device 0x%x not connected?)' % addr)

 	def write(self, data, last):
 		self.wr_reg(self.R_TXR, data);
@@ -80,7 +80,7 @@ class COpenCoresI2C:
 		self.wr_reg(self.R_CR, cmd);
 		self.wait_busy();
 		if(self.rd_reg(self.R_SR) & self.SR_RXACK):
-			raise TpsError('No ACK upon write')
+			raise TpsError('Failed I2C. No ACK upon write')

 	def read(self, last):
 		cmd = self.CR_RD;
@@ -134,8 +134,37 @@ class CSI570 :
 		self.i2c.write(addr, False);
 		self.i2c.start(self.addr, False);
 		return self.i2c.read(True);	
+
+	def calculate_hs(self, hs_div) :
+		convert = {'4': 0, '5': 1, '6': 2, '7':3, '9': 5, '11':7};
+
+		return convert[str(hs_div)];  
+
+
+        def read_setup_oscillator(self) :
+		""" Data saved in internal variables of the class """
+                tmp = self.rd_reg8(self.HS_N1_DIV);
+		self.hs_div = tmp >> 5;
+
+		self.n1 = (tmp & 0x1F) << 2;
+		tmp = self.rd_reg8(self.REF_FREQ_37_32);
+		self.n1 |= tmp >> 6;
+
+		self.rfreq  = (tmp & 0x3F) << 32;
+
+		self.rfreq |= self.rd_reg8(self.REF_FREQ_31_24) << 24;
+		self.rfreq |= self.rd_reg8(self.REF_FREQ_23_16) << 16;
+		self.rfreq |= self.rd_reg8(self.REF_FREQ_15_8)  << 8;
+		self.rfreq |= self.rd_reg8(self.REF_FREQ_7_0);
+
 	
 	def setup_oscillator(self, hs_div, n1_div, rfreq) :
+		""" Setup the oscillator with the given parameters """
+
+		# Freeze the oscillator to setup it
+                self.wr_reg8(self.FREEZE_DCO, (1 << 4));
+
+		# Write setup
 		val = ((hs_div & 0x7) << 5) | (n1_div >> 2)
 		self.wr_reg8(self.HS_N1_DIV, val);

@@ -154,6 +183,51 @@ class CSI570 :
 		val = rfreq & 0xFF;
 		self.wr_reg8(self.REF_FREQ_7_0, val);

+		self.read_setup_oscillator();
+		print "wrote before confirmation"
+	        print "HS DIV: " + str(self.hs_div);
+                print "N1: " + str(self.n1);
+                print "RFREQ: " + str(self.rfreq);
+
+		# Unfreeze it
+		tmp = self.rd_reg8(self.FREEZE_DCO);
+		self.wr_reg8(self.FREEZE_DCO, tmp & 0xEF);
+
+		self.wr_reg8(self.RST_MEM_CTRL, (1 << 6));
+		while(self.rd_reg8(self.RST_MEM_CTRL) & (1 << 6)): 
+			pass;
+
+
+
+        def setup_frequency(self, freq) :
+            """ Calculate the proper parameters and setup them into the oscillator"""
+
+	    finish = 0;
+	    for N1 in range(0,65) :
+	        if N1 == 0 :
+	            n1 = 1;
+                else :
+                    n1 = N1*2;
+
+                for HSDIV in [4, 5, 6, 7, 9, 11] :
+                    x = freq*HSDIV * n1;
+                    if (x < 5670) and (x > 4850) :
+             	         finish = 1;
+                         freq_dco = x;
+	                 break;
+
+	        if finish :
+	            break;
+
+            if (not finish):
+                 raise TpsError('SI570: Not found a proper setup')
+
+            tmp = freq_dco / 114.28;
+            rfreq = int((tmp * (2**28)));
+	    hsdiv = self.calculate_hs(HSDIV);
+	    n1 = n1 - 1;
+            self.setup_oscillator(hsdiv, n1, rfreq);
+
 	def reset(self) :
 		val = (1 << 7);
 		self.wr_reg8(self.RST_MEM_CTRL, val);
@@ -176,9 +250,11 @@ def main (default_directory='.'):

 # The address of the SI570 is fixed in the part number
    si570 = CSI570(i2c, 0x55);
-
-    si570.setup_oscillator(1, 0, 0);
-
+    print "Reading the registers using I2C: "
+    si570.read_setup_oscillator()
+    print "HS DIV: " + str(si570.hs_div);
+    print "N1: " + str(si570.n1);
+    print "RFREQ: " + str(si570.rfreq);
    time.sleep(1)

    if (gennum.iread(0,0x80000,4)) :
@@ -186,6 +262,5 @@ def main (default_directory='.'):
    else :
 	raise TpsError("SIS570 CLK present: FAILED")

-
 if __name__ == '__main__' :
 	main();
--- a/test/spec/python/test07.py
+++ b/test/spec/python/test07.py
-#!   /usr/bin/env   python
+#!/acc/src/dsc/drivers/cohtdrep/siglesia/Python-2.7/python
+#    coding: utf8
+##!   /usr/bin/env   python
 #    coding: utf8

 # Copyright CERN, 2011
@@ -50,62 +52,61 @@ def main (default_directory='.'):
    # Get host memory pages physical address
    pages = gennum.get_physical_addr()

-    num_addr_lines = 64;
+    num_addr_lines = 17;
    num_data_lines = 16;

    if (len(pages) < (num_addr_lines + 2)) :
 	raise Exception("Not enough pages");

+    data = 0xDEADBABA;
    # Clear memory pages
    gennum.set_memory_page(0, 0x0)
-    gennum.set_memory_page(1, 0xFFFFFFFF)
+    gennum.set_memory_page(1, data);
    gennum.set_memory_page(2, 0x0)
-    dma_length = 0x400 # DMA length in bytes
+    dma_length = 0x80 # DMA length in bytes

    t1 = time.time();

    print "Test Address lines"
    print "Checking if some pin is tied to GND"
    error = 0;
+
    for i in range(num_addr_lines) :
+        print "[%d]" % i
+
+	for j in range(num_addr_lines) :

-        gennum.add_dma_item(0, pages[2], dma_length, 1, 1)
-        gennum.add_dma_item(0, pages[3], dma_length, 0, 0)
+            if (i != j) :
+                gennum.add_dma_item((1 << j), pages[2], dma_length, 1, 0)
+                gennum.start_dma()
+                gennum.wait_irq()
+
+        gennum.add_dma_item((1 << i), pages[1], dma_length, 1, 0)
        gennum.start_dma()
        gennum.wait_irq()

-	for j in range(num_addr_lines/2) :
+        # Read all the pages

-            if (i != 2*j) :
-                gennum.add_dma_item((1 << 2*j), pages[2], dma_length, 1, 1)
-                gennum.add_dma_item((1 << 2*j), pages[4+2*j], dma_length, 0, 0)
+	for j in range(num_addr_lines) :
+                gennum.add_dma_item((1 << j), pages[3+j], dma_length, 0, 0)
            	gennum.start_dma()
            	gennum.wait_irq()

-
-            if ((2*j+1) != i) :
-                gennum.add_dma_item((1 << (2*j+1)), pages[2], dma_length, 1, 1)
-                gennum.add_dma_item((1 << (2*j+1)), pages[4+(2*j+1)], dma_length, 0, 0)
-            	gennum.start_dma()
-            	gennum.wait_irq()
-
-        gennum.add_dma_item((1 << i), pages[1], dma_length, 1, 1)
-        gennum.add_dma_item((1 << i), pages[4+i], dma_length, 0, 0)
-        gennum.start_dma()
-        gennum.wait_irq()
                                        
-
+        # Compare
 	page_data = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];
        for j in range(num_addr_lines):
 	    page_data[j] = gennum.get_memory_page(3+j)
-	    if (j == (i + 1)) :
-		if (page_data[j][0] != 0xFFFFFFFF):
-                    print("\n### Compare error (pin is tied to GND?) @ addr line: %d wr:0x%.8X rd:0x%.8X") % (j,0xFFFFFFFF, page_data[j][0])
+	    if (j == i) :
+		if (page_data[j][0] != data):
+                    print("\n### Compare error (pin is tied to GND?) @ addr line: %d wr:0x%.8X rd:0x%.8X") % (j,data, page_data[j][0])
                    error = 1;
            else :
                if(page_data[j][0] != 0x0):
                    print("\n### Compare error (pin is tied to GND?) @ addr line: %d wr:0x%.8X rd:0x%.8X") % (j,0x0, page_data[j][0])
                    error = 1;
+    sys.exit();
+
    print "Checking if some pin is tied to Vcc"

    addr_mask = 0xFFFFFFFFFFFFFFFF;
@@ -123,7 +124,6 @@ def main (default_directory='.'):
            	gennum.start_dma()
            	gennum.wait_irq()

-
            if ((2*j+1) != i) :
                gennum.add_dma_item(addr_mask & (~(1 << 2*j)), pages[2], dma_length, 1, 1)
                gennum.add_dma_item(addr_mask & (~(1 << 2*j)), pages[4+(2*j+1)], dma_length, 0, 0)
@@ -147,7 +147,6 @@ def main (default_directory='.'):
                if(page_data[j][0] != 0x0):
                    print("\n### Compare error (pin is tied to Vcc?) @ addr line:0x%.8X wr:0x%.8X rd:0x%.8X") % (j,0x0, page_data[j][0])
                    error = 1;
-
    if (error) :
 	print "RESULT: [FAILED]"
 	raise TpsError ("Error in DDR address lines. Please check log file for more information")
@@ -179,6 +178,5 @@ def main (default_directory='.'):
    print 'End of test'
    print 'Time DDR test: ' + str(t2-t1) + ' seconds'

-
 if __name__ == '__main__' :
 	main();
--- a/test/spec/python/test09.py
+++ b/test/spec/python/test09.py
+#!   /usr/bin/env   python
+#    coding: utf8
+
+# Copyright CERN, 2011
+# Author: Samuel Iglesias Gonsalvez <siglesia@cern.ch>
+# Licence: GPL v2 or later.
+# Website: http://www.ohwr.org
+
+import sys
+import rr
+import time
+import os
+from ctypes import *
+from tpsexcept import *
+
+"""
+test09: reads serial number of the temperature sensor.
+"""
+
+class COne_wire :
+
+	def __init__ (self,bus, base):
+        	self.base = base;
+        	self.bus = bus;
+		self.serial = self.bus.iread(0, self.base, 4);
+		self.serial |= (self.bus.iread(0, self.base + 4, 4) << 32);
+		
+
+
+def main (default_directory='.'):
+
+	path_fpga_loader = '../firmwares/fpga_loader';
+	path_firmware = '../firmwares/test09.bin';
+    	
+	firmware_loader = os.path.join(default_directory, path_fpga_loader)
+    	bitstream = os.path.join(default_directory, path_firmware)
+    	os.system( firmware_loader + ' ' + bitstream)
+
+    	time.sleep(2);
+    
+	gennum = rr.Gennum();
+    	one_wire = COne_wire(gennum, 0x40000);
+	print "Termometer sensor serial number: " + hex(one_wire.serial)
+
+if __name__ == '__main__' :
+	main();
--- a/test/spec/python/test10.py
+++ b/test/spec/python/test10.py
--- a/test/spec/python/test10_rollback.py
+++ b/test/spec/python/test10_rollback.py
--- a/tps.sh
+++ b/tps.sh
@@ -15,5 +15,5 @@ if [ x$2 = x"" ]; then
 fi


-time ./tps.py -b SPEC -s $serial -e $extra_serial -t./test/spec/python -l /tmp 00 01 02 03 05 06 07 08
+time ./tps.py -b SPEC -s $serial -e $extra_serial -t./test/spec/python -l /tmp 00 01 02 03 04 05 06 07 08 09 10