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Production Test Suite - base
Commit 81af9aa4 authored by Matthieu Cattin's avatar Matthieu Cattin
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Add exceptions and move CSR out of gn4124 module. 

Comments review.
parent 93ee4edb
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Showing with 21 additions and 12 deletions
common/gn4124.py
View file @ 81af9aa4
...@@ -69,6 +69,8 @@ class CGN4124: ...@@ -69,6 +69,8 @@ class CGN4124:
DMA_ATTRIB_LAST = 0 DMA_ATTRIB_LAST = 0
DMA_ATTRIB_DIR = 1 DMA_ATTRIB_DIR = 1
PAGE_SIZE = 4096 # bytes
def rd_reg(self, bar, addr): def rd_reg(self, bar, addr):
return self.bus.iread(bar, addr, 4) return self.bus.iread(bar, addr, 4)
...@@ -152,9 +154,13 @@ class CGN4124: ...@@ -152,9 +154,13 @@ class CGN4124:
# 3 = D4 C3 B2 A1 (invert bytes) # 3 = D4 C3 B2 A1 (invert bytes)
def set_dma_swap(self, swap): def set_dma_swap(self, swap):
if(swap > 3): if(swap > 3):
raise GN4124OperationError('Invalid swapping configuration : %d') % swap raise GN4124OperationError('Invalid swapping configuration : %d' % swap)
else: else:
self.dma_csr.wr_reg(self.R_CTL, (swap << self.DMA_CTL_SWAP)) self.dma_csr.wr_reg(self.R_DMA_CTL, (swap << self.DMA_CTL_SWAP))
# Get DMA byte swapping configuration
def get_dma_swap(self):
return (0x3 & (self.dma_csr.rd_reg(self.R_DMA_CTL) >> self.DMA_CTL_SWAP))
# Add DMA item (first item is on the board, the following in the host memory) # Add DMA item (first item is on the board, the following in the host memory)
# carrier_addr, host_addr, length and next_item_addr are in bytes # carrier_addr, host_addr, length and next_item_addr are in bytes
...@@ -162,7 +168,9 @@ class CGN4124: ...@@ -162,7 +168,9 @@ class CGN4124:
# dma_dir = 0 -> carrier to PCIe # dma_dir = 0 -> carrier to PCIe
# dma_last = 0 -> last item in the transfer # dma_last = 0 -> last item in the transfer
# dma_last = 1 -> more item in the transfer # dma_last = 1 -> more item in the transfer
# Only supports 32-bit host address # Limitations:
# - Only supports 32-bit host address
# - Supports up to 128 items
def add_dma_item(self, carrier_addr, host_addr, length, dma_dir, last_item): def add_dma_item(self, carrier_addr, host_addr, length, dma_dir, last_item):
if(0 == self.dma_item_cnt): if(0 == self.dma_item_cnt):
# write the first DMA item in the carrier # write the first DMA item in the carrier
...@@ -178,14 +186,15 @@ class CGN4124: ...@@ -178,14 +186,15 @@ class CGN4124:
# write nexy DMA item(s) in host memory # write nexy DMA item(s) in host memory
# uses page 0 to store DMA items # uses page 0 to store DMA items
# current and next item addresses are automatically set # current and next item addresses are automatically set
if (self.dma_item_cnt*0x20) > self.PAGE_SIZE:
raise GN4124OperationError('Maximum number of DMA items exceeded!')
current_item_addr = (self.dma_item_cnt-1)*0x20 current_item_addr = (self.dma_item_cnt-1)*0x20
next_item_addr = (self.dma_item_cnt)*0x20 next_item_addr = (self.dma_item_cnt)*0x20
self.wr_reg(self.HOST_BAR, self.HOST_DMA_CARRIER_START_ADDR + current_item_addr, carrier_addr) self.wr_reg(self.HOST_BAR, self.HOST_DMA_CARRIER_START_ADDR + current_item_addr, carrier_addr)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_HOST_START_ADDR_L + current_item_addr, host_addr) self.wr_reg(self.HOST_BAR, self.HOST_DMA_HOST_START_ADDR_L + current_item_addr, host_addr)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_HOST_START_ADDR_H + current_item_addr, 0x0) self.wr_reg(self.HOST_BAR, self.HOST_DMA_HOST_START_ADDR_H + current_item_addr, 0x0)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_LENGTH + current_item_addr, length) self.wr_reg(self.HOST_BAR, self.HOST_DMA_LENGTH + current_item_addr, length)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_L + current_item_addr, self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_L + current_item_addr, self.pages[0] + next_item_addr)
self.pages[0] + next_item_addr)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_H + current_item_addr, 0x0) self.wr_reg(self.HOST_BAR, self.HOST_DMA_NEXT_ITEM_ADDR_H + current_item_addr, 0x0)
attrib = (dma_dir << self.DMA_ATTRIB_DIR) + (last_item << self.DMA_ATTRIB_LAST) attrib = (dma_dir << self.DMA_ATTRIB_DIR) + (last_item << self.DMA_ATTRIB_LAST)
self.wr_reg(self.HOST_BAR, self.HOST_DMA_ATTRIB + current_item_addr, attrib) self.wr_reg(self.HOST_BAR, self.HOST_DMA_ATTRIB + current_item_addr, attrib)
...@@ -195,7 +204,7 @@ class CGN4124: ...@@ -195,7 +204,7 @@ class CGN4124:
def start_dma(self): def start_dma(self):
self.dma_item_cnt = 0 self.dma_item_cnt = 0
self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 1) self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 1)
# The following two lines should be removed # The following lines should be removed
# when the GN4124 vhdl core will implement auto clear of start bit # when the GN4124 vhdl core will implement auto clear of start bit
#while(('Idle' == self.get_dma_status()) or #while(('Idle' == self.get_dma_status()) or
# ('Busy' == self.get_dma_status())): # ('Busy' == self.get_dma_status())):
...@@ -206,20 +215,20 @@ class CGN4124: ...@@ -206,20 +215,20 @@ class CGN4124:
def abort_dma(self): def abort_dma(self):
self.dma_item_cnt = 0 self.dma_item_cnt = 0
self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_ABORT, 1) self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_ABORT, 1)
# The following two lines should be removed # The following lines should be removed
# when the GN4124 vhdl core will implement auto clear of start bit # when the GN4124 vhdl core will implement auto clear of abort bit
while('Aborted' != self.get_dma_status()): #while('Aborted' != self.get_dma_status()):
pass # pass
self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_ABORT, 0) self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_ABORT, 0)
# Get memory page # Get memory page content
def get_memory_page(self, page_nb): def get_memory_page(self, page_nb):
data = [] data = []
for i in range(2**10): for i in range(2**10):
data.append(self.rd_reg(self.HOST_BAR, (page_nb<<12)+(i<<2))) data.append(self.rd_reg(self.HOST_BAR, (page_nb<<12)+(i<<2)))
return data return data
# Set memory page # Set memory page content
def set_memory_page(self, page_nb, pattern): def set_memory_page(self, page_nb, pattern):
for i in range(2**10): for i in range(2**10):
self.wr_reg(self.HOST_BAR, (page_nb<<12)+(i<<2), pattern) self.wr_reg(self.HOST_BAR, (page_nb<<12)+(i<<2), pattern)
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