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Production Test Suite - base
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2ff9a8c4
Commit
2ff9a8c4
authored
Feb 26, 2013
by
Matthieu Cattin
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common:gn4124: Remove dma start but clearing, clear is done already in hw.
parent
f582ba4d
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-1
gn4124.py
common/gn4124.py
+4
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common/gn4124.py
View file @
2ff9a8c4
...
@@ -72,9 +72,11 @@ class CGN4124:
...
@@ -72,9 +72,11 @@ class CGN4124:
PAGE_SIZE
=
4096
# bytes
PAGE_SIZE
=
4096
# bytes
def
rd_reg
(
self
,
bar
,
addr
):
def
rd_reg
(
self
,
bar
,
addr
):
#print("GN4124:READ: bar:0x%1X reg:0x%08X" % (bar,addr))
return
self
.
bus
.
iread
(
bar
,
addr
,
4
)
return
self
.
bus
.
iread
(
bar
,
addr
,
4
)
def
wr_reg
(
self
,
bar
,
addr
,
value
):
def
wr_reg
(
self
,
bar
,
addr
,
value
):
#print("GN4124:WRITE: bar:0x%1X reg:0x%08X data:0x%08X" % (bar,addr,value))
self
.
bus
.
iwrite
(
bar
,
addr
,
4
,
value
)
self
.
bus
.
iwrite
(
bar
,
addr
,
4
,
value
)
def
__init__
(
self
,
bus
,
csr
):
def
__init__
(
self
,
bus
,
csr
):
...
@@ -176,6 +178,7 @@ class CGN4124:
...
@@ -176,6 +178,7 @@ class CGN4124:
# - Only supports 32-bit host address
# - Only supports 32-bit host address
# - Supports up to 128 items
# - Supports up to 128 items
def
add_dma_item
(
self
,
carrier_addr
,
host_addr
,
length
,
dma_dir
,
last_item
):
def
add_dma_item
(
self
,
carrier_addr
,
host_addr
,
length
,
dma_dir
,
last_item
):
#print("GN4124:ADD_DMA_ITEM: item cnt:%d"%self.dma_item_cnt)
if
(
0
==
self
.
dma_item_cnt
):
if
(
0
==
self
.
dma_item_cnt
):
# write the first DMA item in the carrier
# write the first DMA item in the carrier
self
.
dma_csr
.
wr_reg
(
self
.
R_DMA_CARRIER_START_ADDR
,
carrier_addr
)
self
.
dma_csr
.
wr_reg
(
self
.
R_DMA_CARRIER_START_ADDR
,
carrier_addr
)
...
@@ -229,7 +232,7 @@ class CGN4124:
...
@@ -229,7 +232,7 @@ class CGN4124:
#while(('Idle' == self.get_dma_status()) or
#while(('Idle' == self.get_dma_status()) or
# ('Busy' == self.get_dma_status())):
# ('Busy' == self.get_dma_status())):
# pass
# pass
self
.
dma_csr
.
wr_bit
(
self
.
R_DMA_CTL
,
self
.
DMA_CTL_START
,
0
)
#
self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 0)
# Abort DMA transfer
# Abort DMA transfer
def
abort_dma
(
self
):
def
abort_dma
(
self
):
...
...
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