Skip to content

P
PPSi
Commit f13b2ae9 authored by li hongming's avatar li hongming
Browse files
Options

Add a new CONFIG parameter CONFIG_DUALPORT.

parent 61d931c0
Hide whitespace changes
Inline Side-by-side
Showing with 76 additions and 43 deletions
Makefile
View file @ f13b2ae9
......@@ -83,6 +83,7 @@ CFLAGS += -DDEFAULT_TIME_OPS=$(TIME)_time_ops
CFLAGS += -DDEFAULT_NET_OPS=$(TIME)_net_ops
CFLAGS-$(CONFIG_ABSCAL) += -DCONFIG_ABSCAL=1
CFLAGS-$(CONFIG_DUALPORT) += -DCONFIG_DUALPORT=1
CFLAGS += $(CFLAGS-y)
export CFLAGS
......
arch-wrpc/wrc_ptp_ppsi.c
View file @ f13b2ae9
......@@ -26,7 +26,7 @@
extern int32_t cal_phase_transition[wr_num_ports];
int ptp_mode = WRC_MODE_UNKNOWN;
static int ptp_enabled[wr_num_ports] = {0,0};
static int ptp_enabled[wr_num_ports];
static struct wr_operations wrpc_wr_operations = {
.locking_enable = wrpc_spll_locking_enable,
......@@ -56,24 +56,24 @@ static DSTimeProperties timePropertiesDS;
static struct pp_servo servo;
static struct wr_servo_state servo_state;
static struct wr_dsport wr_dsport[wr_num_ports] = {
static struct wr_dsport wr_dsport[] = {
{.ops = &wrpc_wr_operations,},
{.ops = &wrpc_wr_operations,}
};
static DSPort portDS[wr_num_ports] = {
static DSPort portDS[] = {
{.ext_dsport = &wr_dsport[0],},
{.ext_dsport = &wr_dsport[1],}
};
static int delay_ms[wr_num_ports] = {PP_DEFAULT_NEXT_DELAY_MS,PP_DEFAULT_NEXT_DELAY_MS};
static int start_tics[wr_num_ports] = {0,0};
static int delay_ms[] = {PP_DEFAULT_NEXT_DELAY_MS,PP_DEFAULT_NEXT_DELAY_MS};
static int start_tics[wr_num_ports];
static struct pp_globals ppg_static; /* forward declaration */
static unsigned char __tx_buffer[wr_num_ports][PP_MAX_FRAME_LENGTH];
static unsigned char __rx_buffer[wr_num_ports][PP_MAX_FRAME_LENGTH];
/* despite the name, ppi_static is not static: tests/measure_t24p.c uses it */
struct pp_instance ppi_static[wr_num_ports] = {
struct pp_instance ppi_static[] = {
// port 0
{.glbs = &ppg_static,
.portDS = &portDS[0],
......@@ -114,6 +114,7 @@ static struct pp_globals ppg_static = {
int wrc_ptp_init()
{
int port;
sdb_find_devices();
uart_init_hw();
......@@ -122,9 +123,11 @@ int wrc_ptp_init()
struct pp_globals *ppg = &ppg_static;
ppg->pp_instances[0] = ppi_static[0];
ppg->pp_instances[1] = ppi_static[1];
for (port = 0; port < wr_num_ports; ++port)
{
ppg->pp_instances[port] = ppi_static[port];
ptp_enabled[port] = 0;
}
pp_init_globals(ppg, &__pp_default_rt_opts);
return 0;
......@@ -138,11 +141,13 @@ int wrc_ptp_set_mode(int mode)
uint32_t start_tics, lock_timeout = 0;
struct pp_globals *ppg = &ppg_static;
struct pp_instance *ppi[wr_num_ports];
ppi[0] = INST(ppg, 0);
ppi[1] = INST(ppg, 1);
struct wr_dsport *wrp[wr_num_ports];
wrp[0] = WR_DSPOR(ppi[0]);
wrp[1] = WR_DSPOR(ppi[1]);
int port;
for (port = 0; port < wr_num_ports; ++port)
{
ppi[port] = INST(ppg, port);
wrp[port] = WR_DSPOR(ppi[port]);
}
typeof(ppg->rt_opts->clock_quality.clockClass) *class_ptr;
int error = 0;
......@@ -154,47 +159,52 @@ int wrc_ptp_set_mode(int mode)
ptp_mode = 0;
wrc_ptp_stop(0);
wrc_ptp_stop(1);
ppi[0]->cfg.ext = PPSI_EXT_WR; // Enable WR mode
ppi[1]->cfg.ext = PPSI_EXT_WR;
for (port = 0; port < wr_num_ports; ++port) {
wrc_ptp_stop(port);
ppi[port]->cfg.ext = PPSI_EXT_WR; // Enable WR mode
}
switch (mode) {
case WRC_MODE_GM:
case WRC_MODE_ABSCAL: /* absolute calibration, gm-lookalike */
wrp[0]->wrConfig = WR_M_ONLY;
wrp[1]->wrConfig = WR_M_ONLY;
ppi[0]->role = PPSI_ROLE_MASTER;
ppi[1]->role = PPSI_ROLE_MASTER;
for (port = 0; port < wr_num_ports; ++port) {
wrp[port]->wrConfig = WR_M_ONLY;
ppi[port]->role = PPSI_ROLE_MASTER;
}
*class_ptr = PP_CLASS_WR_GM_LOCKED;
spll_init(SPLL_MODE_GRAND_MASTER, 0, 1);
shw_pps_gen_unmask_output(1);
lock_timeout = LOCK_TIMEOUT_GM;
DSDEF(ppi[0])->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
DSDEF(ppi[1])->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
for (port = 0; port < wr_num_ports; ++port) {
DSDEF(ppi[port])->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
}
m1(ppi[0]); // port0 and por1 share one pp_global
break;
case WRC_MODE_MASTER:
wrp[0]->wrConfig = WR_M_ONLY;
wrp[1]->wrConfig = WR_M_ONLY;
ppi[0]->role = PPSI_ROLE_MASTER;
ppi[1]->role = PPSI_ROLE_MASTER;
for (port = 0; port < wr_num_ports; ++port) {
wrp[port]->wrConfig = WR_M_ONLY;
ppi[port]->role = PPSI_ROLE_MASTER;
}
*class_ptr = PP_CLASS_DEFAULT;
spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, 1);
shw_pps_gen_unmask_output(1);
lock_timeout = LOCK_TIMEOUT_FM;
DSDEF(ppi[0])->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
for (port = 0; port < wr_num_ports; ++port) {
DSDEF(ppi[port])->clockQuality.clockClass = PP_CLASS_WR_GM_LOCKED;
}
m1(ppi[0]);
break;
case WRC_MODE_SLAVE:
wrp[0]->wrConfig = WR_S_ONLY;
wrp[1]->wrConfig = WR_M_ONLY;
ppi[0]->role = PPSI_ROLE_SLAVE;
ppi[1]->role = PPSI_ROLE_MASTER;
if (wr_num_ports>1)
{
wrp[1]->wrConfig = WR_M_ONLY;
ppi[1]->role = PPSI_ROLE_MASTER;
}
// *class_ptr = PP_CLASS_SLAVE_ONLY;
*class_ptr = PP_CLASS_DEFAULT;
spll_init(SPLL_MODE_SLAVE, 0, 1);
......@@ -250,7 +260,7 @@ int wrc_ptp_sync_mech(int e2e_p2p_qry)
return 0;
default:
return ppi->mech;
}
};
}
int wrc_ptp_start(int port)
......@@ -267,8 +277,11 @@ int wrc_ptp_start(int port)
start_tics[port] = timer_get_tics();
WR_DSPOR(ppi)->linkUP = FALSE;
wr_servo_reset(ppi);
ptp_enabled[port] = 1;
switch(port) {
case 0: ptp_enabled[port] = 1; break;
case 1: ptp_enabled[port] = 2; break;
default:ptp_enabled[port] = 1;
}
return 0;
}
......@@ -280,7 +293,7 @@ int wrc_ptp_stop(int port)
ppi = INST(ppg, port);
wrp = WR_DSPOR(ppi);
pp_printf("Port %d PTP stop",port);
pp_printf("Port %d PTP stop\n",port);
/* Moving fiber: forget about this parent (FIXME: shouldn't be here) */
wrp->parentWrConfig = wrp->parentWrModeOn = 0;
memset(ppi->frgn_master, 0, sizeof(ppi->frgn_master));
......@@ -295,17 +308,32 @@ int wrc_ptp_stop(int port)
int wrc_ptp_run(int start_stop_query)
{
int port;
int ptp_enabled_sum=0;
switch(start_stop_query) {
case 0:
wrc_ptp_stop(0);
wrc_ptp_stop(1);
for (port = 0; port < wr_num_ports; ++port){
wrc_ptp_stop(port);
}
return 0;
case 1:
wrc_ptp_start(0);
wrc_ptp_start(1);
if(wr_num_ports>1)wrc_ptp_stop(1);
return 0;
case 2:
wrc_ptp_stop(0);
if(wr_num_ports>1)wrc_ptp_start(1);
return 0;
case 3:
for (port = 0; port < wr_num_ports; ++port){
wrc_ptp_start(port);
}
return 0;
default:
return (ptp_enabled[0] || ptp_enabled[1]);
for (port = 0; port < wr_num_ports; ++port){
ptp_enabled_sum += ptp_enabled[port];
}
return ptp_enabled_sum;
}
}
......
arch-wrpc/wrpc-spll.c
View file @ f13b2ae9
......@@ -13,7 +13,7 @@
#include <rxts_calibrator.h>
#include "wrpc.h"
extern uint32_t cal_phase_transition[wr_num_ports];
extern uint32_t cal_phase_transition[];
int wrpc_spll_locking_enable(struct pp_instance *ppi)
{
......
include/ppsi/ppsi.h
View file @ f13b2ae9
......@@ -338,8 +338,6 @@ extern int pp_config_file(struct pp_globals *ppg, int force, char *fname);
extern int f_simple_int(struct pp_argline *l, int lineno,
struct pp_globals *ppg, union pp_cfg_arg *arg);
#define wr_num_ports 2
#define PPSI_PROTO_RAW 0
#define PPSI_PROTO_UDP 1
#define PPSI_PROTO_VLAN 2 /* Actually: vlan over raw eth */
......@@ -431,4 +429,10 @@ extern void ppsi_drop_init(struct pp_globals *ppg, unsigned long seed);
extern int ppsi_drop_rx(void);
extern int ppsi_drop_tx(void);
#ifdef CONFIG_DUALPORT
#define wr_num_ports 2
#else
#define wr_num_ports 1
#endif
#endif /* __PPSI_PPSI_H__ */
time-wrpc/wrpc-socket.c
View file @ f13b2ae9
......@@ -27,7 +27,7 @@ int frame_rx_delay_us; /* set by faults.c */
static uint8_t __ptp_queue[wr_num_ports][512];
static struct wrpc_socket __static_ptp_socket[wr_num_ports] = {
{.queue.buff = __ptp_queue[0],
.queue.size = sizeof(__ptp_queue),},
.queue.size = sizeof(__ptp_queue[0]),},
{.queue.buff = __ptp_queue[1],
.queue.size = sizeof(__ptp_queue[1]),}
};
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment