Add MN design for Altera C5 SoC development board with Nios II as PCP
and HPS ARM as host processor. The FPGA DDR memory is used as a shared
memory for ARM and Nios II.
- Create Quartus 14.0 project files
- Create Qsys design with Nios II (PCP) and HPS/ARM
- Create dualprocshm memory configuration header
- Create CMake setting files for ARM
- Create setting file for Nios II
- Add linker files for ARM semihosted and unhosted application build
- Update the boards ignore file for generated files and directories
- Add DS5 debugger script for Altera ARM for hosted and semihosted
  operation.

Change-Id: Ibafccd285bfc848b4c5dd1ceb67ca2259ccbd4fd