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OPT ADC 10k 32b 1cha (HPM7177)

Project description

The OPT ADC 10k 32b 1cha is a single channel 10kSPS 32 bit ADC card in the format defined by the CERN TE-EPC group for use with the Function Generator Controller (FGC 3.2) . It is also known under the name HPM7177.

The device is a metrology-grade ADC for the highest accuracy class in the HL-LHC accelerator. CERN will need over a hundred.

The design is based on a commercial ADC, the Analog Device AD7177-2. It is a standalone unit that interfaces through an optical fibre for the read-out and synchronization. The target analog signal bandwidth is 2000 Hz, and the main design objectives are very low 1/f noise and excellent short-term stability and accuracy with an effective resolution over 23 bits for a bandwidth below 10 Hz.

In the second half of 2019 several prototypes were produced and tested. Based on this feedback, a revised version (V2) was prepared in 2020. In 2022 a full metrological characterization of the device was carried out. A commercial contract for the production of more than 100 units was signed in 2022, and the first units were delivered in 2023.

A block diagram of the device is available here

Left: Fully assembled device Right: Open unit with ADC mezzanine removed

Other images: Bottom side of the ADC mezzanine board - Test setup with 4 units in a climatic chamber

Specifications

Parameter Value
ADC device Analog Devices AD7177-2
ADC type 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail Buffers
bits/sample 32 bit
effective resolution >23 bits for BW < 10 Hz
short-term stability >25 bits (<20 parts-per-billion)
temperature drift (offset and gain) <0.1 ppm/°C from 20°C to 40°C
INL <0.6 ppm (0 to +10 V)
SNR >120 dB at 500 Hz bandwidth
max. sample rate 10 kSPS
analog bandwidth 5 kHz, DC-coupled
channels 1
connectors 1 x LEMO 0B.302 for input signal
input impedance 10 MOhm (differential), 5 MOhm (common-mode)
DC CMRR >120 dB
input range +/-10 V nominal with 30% over-range
backplane interface only for power, ID and production test
Read-out interface plastic optical fibre, bi-directional
USB (optional)
Clock source External: synchronization pulses over optical fibre / Internal

Project Information

Contacts

Commercial producers

Norcott Technologies Ltd. (Widnes, UK) won the tender for production of >100 units for HL-LHC. Pre-series units were delivered in the end of 2022.

General question about project

Status

Date Event
04-05-2018 Start working on project. First prototype design expected in second half 2019.
20-12-2019 First prototype series evaluated.
27-01-2020 POSTPONED DUE TO COVID-19. Characterization tests will be done in PTB, the National Metrology Institute of Germany.
19-02-2020 Added link to 13.02.2020 Hi Lumi TCC talk
03-03-2020 Added datasheets of Vishay resistor arrays
11-03-2020 Block diagram added.
30-03-2020 Added link to Accelerating News article on HPM7177 (local file copy is here)
17-08-2020 Added links to V2 documentation (HPM7177) and the power supply (V1) and 19" chassis (V1).
18-08-2020 Block diagram updated to V2
10-12-2020 Added link to EPC group talk on HPM7177
07-01-2021 Added link to EDA for the mechanical part used for special component mounting EDA-04088-V1
07-01-2021 Removed links to old versions of documentation
20-07-2021 Updated links: V3 (ADC module); V3 (ADC mezzanine); V2 (grounding board); V2 (PSU)
29-09-2021 Updated link to V2 of EDA-04258 (19" chassis)
08-12-2021 Updated link to V4 of EDA-04061 (ADC mezzanine)
20-06-2022 Added links to I2MTC proceedings papers
21-03-2023 Updated links: V4 (ADC module); V4-1 (ADC mezzanine), V3 (PSU), V3 (19" chassis)
12-03-2024 Added links to Bratislava presentation and IEEE TIM paper
12-03-2024 First six units of HPM7177 installed and commissioned in the SPS mains (circuits MBI, QD, QF)

12 March 2024