WISHBONE signals
WISHBONE STB and ACK
When nanoFIP detects a rising edge on the STB_I signal, it checks:
- If the CYC_I signal is asserted and
- If the address provided ADR_I belongs to the Produced memory block and the WE_I is enabled or if the address provided belongs to the Consumed memory block and the WE_I is disabled.
If so, it asserts the ACK_O for 1 wclk cycle.
Note: nanoFIP is synchronizing the WISHBONE control signals with triple buffers, therefore an ACK_O pulse appears 4 wclk cycles after the STB_I rising edge.
WISHBONE read, control
signals
WISHBONE write, control signals
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E.Gousiou, March 2012